TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A – DECEMBER 1994 – REVISED AUGUST 1995
6–16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
voltage transitioning requirement (continued)
capacitors on 3.3-V compatible cards be discharged to below 0.8 V before applying 3.3-V power. This ensures
that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power reset. The
TPS2202 offers a selectable V
CC
and V
PP
ground state, in accordance with PCMCIA 3.3-V/5-V switching
specifications, to fully discharge the card capacitors while switching between V
CC
voltages.
output ground switches
Several PCMCIA power-distribution switches on the market do not have an active-grounding FET switch. These
devices do not meet the PC Card specification requiring a discharge of V
CC
within 100 ms. PC Card resistance
can not be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible
high-impedance isolation by power-management schemes. A method commonly shown to alleviate this
problem is to add to the switch output an external 100 k
resistor in parallel with the PC Card. Considering that
this is the only discharge path to ground, a timing analysis will reveal that the RC time constant delays the
required discharge time to over 2 seconds. The only way to ensure timing compatibility with PC Card standards
is to use a power-distribution switch that has an internal ground switch, like that of the TPS22xx family, or add
an external ground FET to each of the output lines with the control logic necessary to select it.
In summary, the TPS2202 is a complete single-chip dual-slot PC Card power interface. It meets all currently
defined PCMCIA specifications for power delivery in 5-V, 3.3-V, and mixed systems, and offers a serial controller
interface. The TPS2202 offers functionality, power savings, overcurrent and thermal protection, and fault
reporting in one 30-pin SSOP surface-mount package for maximum value added to new portable designs.
power supply considerations
The TPS2202 has multiple terminals for each of its 3.3 V, 5 V, and 12 V power inputs and for the switched V
CC
outputs. Any individual terminal can conduct the rated input or output current. Unless all terminals are connected
in parallel, the series resistance is significantly higher than that specified, resulting in increased voltage drops
and lost power. Both 12 V inputs must be connected for proper V
pp
switching; it is recommended that all input
and output power terminals be paralleled for optimum operation. The V
DD
input lead must be connected to the
5V input leads.
Although the TPS2202 is fairly immune to power input fluctuations and noise, it is generally considered good
design practice to bypass power supplies typically with a 1-
μ
F electrolytic or tantalum capacitor paralleled by
a 0.047-
μ
F to 0.1-
μ
F ceramic capacitor. It is strongly recommended that the switched V
CC
and V
pp
outputs be
bypassed with a 0.1-
μ
F or larger capacitor; doing so improves the immunity of the TPS2202 to electrostatic
discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the TPS2202 and
the load. High switching currents can produce large negative-voltage transients, which forward biases substrate
diodes, resulting in unpredictable performance.
The TPS2202, unlike other PC Card power-interface switches, does not use the 12-V power supply for switching
or other chip functions. Instead, an internal charge pump generates the necessary voltage from V
DD
, allowing
the 12-V input supply to be shut down except when the V
pp
programming or erase voltage is needed. Careful
system design making use of this feature reduces power consumption and extends battery lifetime.
The 3.3-V power input should not be taken higher than the 5-V input. Doing so, though nondestructive, results
in high current flow into the device, and could result in abnormal operation. In any case, this occurrence indicates
a malfunction of one input voltage or both, which should be investigated.
Similarly, no terminal should be taken below –0.3 V; forward biasing the parasitic-substrate diode results in
substrate currents and unpredictable performance.