TPS2204A
TPS2206A
TPS2210A
SLVS449A DECEMBER 2002 REVISED MAY 2003
www.ti.com
21
SHUTDOWN MODE
In the shutdown mode, which can be controlled by SHDN or bit D8 of the input serial DATA word, each of the xVCC and
xVPP outputs is forced to a high-impedance state. In this mode, the chip quiescent current is reduced to 1
A or less to
conserve battery power.
POWER-SUPPLY CONSIDERATIONS
These switches have multiple pins for each 3.3-V (except for the TPS2210A) and 5-V power input and for the switched
xVCC outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel,
the series resistance is higher than that specified, resulting in increased voltage drops and power loss. It is recommended
that all input and output power pins be paralleled for optimum operation.
To increase the noise immunity of the TPS2204A, TPS2206A, and TPS2210A, the power-supply inputs should be
bypassed with at least a 4.7-
F electrolytic or tantalum capacitor paralleled by a 0.047-F to 0.1-F ceramic capacitor. It
is strongly recommended that the switched outputs be bypassed with a 0.1-
F (or larger) ceramic capacitor; doing so
improves the immunity of the IC to electrostatic discharge (ESD). Care should be taken to minimize the inductance of PCB
traces between the devices and the load. High switching currents can produce large negative voltage transients, which
forward biases substrate diodes, resulting in unpredictable performance. Similarly, no pin should be taken below 0.3 V.
RESET INPUT
To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should be reset at
the same time as the host by applying low-impedance paths from xVCC and xVPP terminals to ground. A low-impedance
output state allows discharging of residual voltage remaining on PC Card filter capacitance, permitting the system (host
and PC Cards) to be powered up concurrently. The active low RESET input closes internal ground switches S1, S4, S7,
and S11 with all other switches left open. The devices remain in the low-impedance output state until the signal is
deasserted and new data is clocked in and latched. The input serial data cannot be latched during reset mode. RESET
is provided for direct compatibility with systems that use an active-low reset voltage supervisor. The RESET pin has an
internal 150-k
pullup resistor.
CALCULATING JUNCTION TEMPERATURE
The switch resistance, rDS(on), is dependent on the junction temperature, TJ, of the die. The junction temperature is
dependent on both rDS(on) and the current through the switch. To calculate TJ, first find rDS(on) from Figures 26 through 28,
using an initial temperature estimate about 30
°C above ambient. Then calculate the power dissipation for each switch,
using the formula:
P
D +
r
DS(on)
I2
Next, sum the power dissipation of all switches and calculate the junction temperature:
T
J +
P
D
RqJA ) TA,RqJA + 108°C W
Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not within a few
degrees of each other, recalculate using the calculated temperature as the initial estimate.