參數(shù)資料
型號: TPS2340APFPRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: 2-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP80
封裝: GREEN, PLASTIC, HTQFP-80
文件頁數(shù): 29/29頁
文件大?。?/td> 578K
代理商: TPS2340APFPRG4
TPS2340A
SLUS528A MARCH 2002 REVISED AUGUST 2002
9
www.ti.com
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
RESETA
35
O
PCI RESET signal to slot A. Conforms to PCI 2.2 local bus specification for 3.3-V signaling. This pin is
typically tied to the PCI connector.
RESETB
26
O
PCI RESET signal to slot B. Conforms to PCI 2.2 local bus specification for 3.3-V signaling. This pin is
typically tied to the PCI connector.
SIC
44
I
Serial input clock. Shift serial data into device one bit position on rising edge.
SIDI
20
I
Serial input data Input. The serial shift register input from a down-stream TPS2340.
SIDO
41
I/O
Serial input data output. The serial shift register output to the PCI hot-plug controller or the up-stream
TPS2340. When PGOOD is low, SIDO is undriven and pulled up to DIGVCC with a 100-k
resistor.
During the rising edge of PGOOD, the TPS2340A latches SIDO as MODE0.
SIL
16
I
Serial input load. Pulse low to synchronously parallel load external serial input shift registers on the
next rising edge of SIC.
SOC
17
I
Serial output clock. Shift serial output data into parallel output registers one bit position on rising edge.
SODI
42
I
Serial output data input. Serial output data shifted into parallel output registers.
SODO
19
I/O
Serial output data output. Serial output data shifted to the down-stream TPS2340. When PGOOD is
low, SODO is undriven and pulled up to DIGVCC with a 100-k
resistor. During the rising edge of
PGOOD, the TPS2340A latches SODO as MODE1.
SOLC
39
I
Serial output latch clock. Latch parallel register data on rising edge.
SORLC
22
I
Serial output reset latch clock. Latch parallel register data on rising edge (PCI RESET latches only).
SOR
40
I
Serial output reset. Clears parallel register data.
SORR
21
I
Serial output reset reset. Clears parallel register data (PCI RESET latches only).
SWA
46
I
Slot A switch input. Low indicates the slot is populated. This input has hysteresis and a 100-k
pull-up
to 3VAUXI, requiring only a capacitor to ground for debouncing mechanical noise. For testing pur-
poses, pulling SWA to 5 V enables the slot main power and disables the slot auxilliary power, bypass-
ing the serial interface.
SWB
14
I
Slot B switch input. Low indicates the slot is populated. This input has hysteresis and a 100-k
pull-up
to 3VAUXI, requiring only a capacitor to ground for debouncing mechanical noise. For testing pur-
poses, pulling SWB to 5 V enables the slot main power and disables the slot auxilliary power, bypass-
ing the serial interface.
TEST
23
I
When asserted on the rising edge of PGOOD, device enters test modes based on the states of the
MODE pins. See InCircuit Test section of the datasheet. When asserted after PGOOD is asserted,
maps the Pwrenx and ANDed Faultx internal signals to PWRLED and ATTLED pins for test purposes.
TEST has a 100-k
pull-down resistor to ground.
V5IN
49
I
5-V input to the device. A 0.1-
F bypass capacitor from V5IN to PWRGND is recommended.
相關(guān)PDF資料
PDF描述
TPS2341PHPR 4-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48
TPS2343DDPG3 6-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO80
TPS2343DDPR 6-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO80
TPS2345PWNRND 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24
TPS2346PWG4 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24
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