參數(shù)資料
型號(hào): TPS2341PHPR
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): 電源管理
英文描述: 4-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48
封裝: POWERPAD, HTQFP-48
文件頁(yè)數(shù): 15/31頁(yè)
文件大小: 649K
代理商: TPS2341PHPR
TPS2341
SLUS513A MAY 2003 REVISED JULY 2004
22
www.ti.com
APPLICATION INFORMATION
Test Mode Functions for Address Bit
The TPS2341 address pin (ADDR1) provides two functions. The input provides the I2C serial interface with a
unique address when two TPS2341 devices share the same address bank and also provides a means of
disabling faults. Three different voltage levels are used to define the status of the input signal. Upon pulling the
address pin low, the serial interface address bit is set low. The serial interface address bit is set high if the
address pin is allowed to float or is driven to one-half the voltage at DIGVCC. Upon pulling ADDR1 to DIGVCC
the internal test mode is invoked which masks the overload and undervoltage faults and does not shut down
the slots when the thresholds are exceeded. This is intended to be used for board development only to avoid
nuisance faults from improperly sized bulk capacitance or excessive switching loads. Caution must be taken
to never exceed the maximum dissipation or absolute maximum conditions of the device while the device
self-protection is disabled.
Table 2. I2C Device Address Decode
BIT
DEFINITION
A0
R/W bit
0: Write data from master to TPS2341
1: Read data from TPS2341 to master
A1
Device address bit 1 (LSB) compared with pin ADDR1
A2
0 internally defined
A3
0 internally defined
A4
0 internally defined
A5
0 internally defined
A6
1 internally defined
A7
0 internally defined
Table 3. Test Mode Functions for Adddress Bits
BIT
VOLTAGE
LEVEL (V)
ADDRESS
FUNCTION
TEST MODE
FUNCTION
< 0.8
Low
OFF
A1
0.8 < VA1 < 2.5
High
OFF
A1
> 2.5
High
Mask fault active
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