參數(shù)資料
型號(hào)： TPS2359RHHT
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC36
封裝： 6 X 6 MM, GREEN, PLASTIC, QFN-36
文件頁(yè)數(shù)： 18/53頁(yè)
文件大?。?/td> 1074K
代理商： TPS2359RHHT
www.ti.com
SLUS792F – FEBRUARY 2008 – REVISED AUGUST 2010
Register 6
Table 9. Register 6: System Configuration (Read/write)
BIT
NAME
DEFAULT
DESCRIPTION
0
PPTEST
0
12-V pulldown test pin. Asserting this pulls the PASSx and BLKx pins to 0 V.
Clearing bit forces channels to latch off after over-current fault. Setting bit allows
1
FLTMODE
0
channels to automatically attempt restart after fault.
2
SPARE
0
This bit must always be set to 0.
Setting bit enables 3A and 3B to prevent reverse current flow.Clearing bit disables 3A
3
3ORON
0
and 3B ORing.
Non Redundant System in rush control bit. Setting bit allows increased inrush current
4
12VNRS
0
in 12A and 12B.
5
AIRM
0
Setting this masking bit prevents REG7 bits 3:0 from setting IRPT.
6
BIRM
0
Setting this masking bit prevents REG7 bits 7:4 from setting IRPT.
Setting bit allows the 12 V channels to operate despite loss of 3.3 V. For uTCA and
7
DCC
0
AMC applications this bit should be low.
PPTEST This bit is used for testing the fast turnoff feature of the PASSx and BLKx pins. Setting this bit enables
the fast turnoff drivers for all four pins. Clearing this bit restores normal operation. PPTEST allows the fast turnoff
drivers to operate at full current indefinitely, whereas they would normally operate for only about 15 S. While
using PPTEST the energy dissipated in the fast turnoff drivers must be externally limited to 1 mJ per driver to
prevent damage to the TPS2359.
FLTMODE Setting this bit allows a channel to attempt an automatic restart after an overcurrent condition has
caused it to time out and shut off. The retry interval equals approximately 100 times the programmed fault time.
The FLTMODE bit affects all four channels. If cross-connection is enabled (DCC = 0), a fault on channel 3A turns
off channel 12A, and a fault on channel 3B turns off channel 12B. If a 3.3-V channel automatically restarts
because FLTMODE = 1, the associated 12-V channel remains disabled until its enable bit (12AEN or 12BEN) is
cycled on and off.
SPARE This bit must always be set to 0.
3ORON Setting this bit allows the 3.3-V ORing function to operate normally. Clearing this bit prevents the 3.3-V
channels from disabling if their output voltage exceeds their input voltage . This bit is typically cleared for
non-redundant systems.
12VNRS Setting this bit increases the current limit for either 12-V channel to its maximum value during the initial
inrush period that immediately follows the enabling of the channel. During inrush, the current limit behaves as if
12xCL[3:0] = 1111B. After the current drops below this limit, signifying the end of the inrush period, the current
limit returns to normal operation.
AIRM Setting this bit prevents the 12APG, 12AFLT, 3APG, and 3AFLT bits from setting the IRPT pin.
BIRM Setting this bit prevents the 12APG, 12BFLT, 3BPG, and 3BFLT bits from setting the IRPT pin.
DCC Setting this bit disables cross-connection. If DCC = 0, when a 3.3-V channel experiences a fault, both it and
its associated 12-V channel turn off. Specifically, a fault on channel 3A turns off channel 12A, and a fault on
channel 3B turns off channel 12B. If DCC = 1, then the 12-V channels continue to operate even if their
associated 3.3-V channels experience faults.
Copyright 2008–2010, Texas Instruments Incorporated
25
Product Folder Link(s): TPS2359
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