www.ti.com
Load Capacitor
Transient Suppressor
Layout
SLVS646A – SEPTEMBER 2006 – REVISED SEPTEMBER 2006
APPLICATION INFORMATION (continued)
The IEEE 802.3af specification requires that the PD maintain a minimum load capacitance of 5
F.
A PD can fail the dc MPS requirement if the load current to capacitance ratio is too small. This is caused by
having a long input current dropout after a drop in input voltage. The PD should begin to draw input current
within 300 ms of an abrupt 13 V input droop.
A particular design may have a tendency to cause ringing at the RTN pin during startup, inadvertent hot-plugs of
the PoE input, or plugging in a wall adapter. It is recommended that a minimum value of 1
F be used at the
output of the TPS2376-H if downstream filtering prevents placing the larger bulk capacitor right on the output.
When using ORing option 2, it is recommended that a large capacitor such as a 22
F be placed across the
TPS2376-H output.
Voltage transients on the TPS2376-H can be caused by connecting or disconnecting the PD, or by other
environmental conditions like ESD. A transient voltage suppressor, such as the SMAJ58A, should be installed
after the bridge and across the TPS2376-H input as shown in
Figure 1.Some form of protection may be required from V(VDD-RTN) if adequate capacitance is not present. RTN is a high
impedance node when the MOSFET is off. Some topologies may cause large transients to occur on this pin
when the PD is plugged into an active supply.
The layout of the PoE front end must use good practices for power and EMI/ESD. A basic set of
recommendations include:
1. The parts placement must be driven by the power flow in a point-to-point manner such as RJ-45
→ Ethernet
interface
→ diode bridges → TVS and 0.1-F capacitor → TPS2376-H → output capacitor.
2. There should not be any crossovers of signals from one part of the flow to another.
3. All leads should be as short as possible with wide power traces and paired signal and return.
4. Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltage
rails and between the input and an isolated converter output.
5. The TPS2376-H should be over a local ground plane or fill area referenced to VSS.
6. Large SMT component pads should be used on power dissipating devices such as the diodes and the
TPS2376-H.
Use of generous copper area on VSS and to help the PCB spread and dissipate the heat is recommended.
Assuming a worst-case power dissipation of 0.4 W, the required thermal resistance may be calculated as:
θ
JA = (
tJ_MAX - tA_MAX ) / P. A thermal resistance of 50°C/W is required for a junction temperature of 105°C at an
ambient of 85
°C. The effect of additional local heating on the circuit board from other devices must be
considered. The thermal resistance cases provided in the dissipation rating table should be used as a guide in
determining the required area.
Figure 15 provides an example of a single sided layout with liberal copper plane areas to help spread the heat.
The active circuit area could be reduced by locating the small resistors on the backside of the board. The
TPS2376-H PowerPad is covered by copper fill, which has multiple vias to a backside mirror-image fill. There
are 5 small vias under the PowerPad per the guidelines of SLMA0002 which are masked by the graphics of the
tool. The fills for RTN and VDD also help spread the heat. A copper fill clearance of 0.030 inches was used for
VDD to RTN or VSS. A spacing of 0.025 inches for the full PoE voltage was met elsewhere.
15