參數(shù)資料
型號(hào)： TPS2393APWRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO14
封裝： GREEN, PLASTIC, TSSOP-14
文件頁(yè)數(shù)： 26/30頁(yè)
文件大?。?/td> 665K
代理商： TPS2393APWRG4
TPS2393A
SLUS610 JULY 2004
5
www.ti.com
PIN ASSIGNMENTS
DRAINSNS: Sense input for monitoring the load voltage status. The DRAINSNS pin determines the load status
by sensing the voltage level on the external pass FET drain. DRAINSNS must be pulled low with repect to VIN
(less than 1.35 V typically) to declare a power good condition. This corresponds to a low VDS across the FET,
indicating that the load voltage has successfully ramped up to the DC input level. DRAINSNS must be connected
to the FET drain through a small-signal blocking diode as shown in the typical application diagram. An internal
pull-up maintains a high logic level at the pin until overridden by a fully-enhanced external FET.
EN: Enable input to turn on/off power to the load. The EN pin is referenced to the VIN potential of the circuit.
When this input is pulled high (above the nominal 1.4-V threshold), and all other input qualifications are met
(supply above device undervoltage lockout (UVLO), UVLO pin high and OVLO pin low, INSx pins pulled low)
the device enables the GATE output, and begins the ramp of current to the load. When this input is low, the linear
current amplifier (LCA) is disabled, and a large pull-down device is applied to the FET gate, disabling power
to the load.
FAULT: Open-drain, active-low indication of a load fault condition. When the device EN is deasserted, or when
enabled and the load current is less than the programmed limit, this output is high impedance. If the device
remains in current regulation mode at the expiration of the fault timer, the fault is latched, the load is turned off,
and the FAULT pin is pulled low (to VIN). The TPS2393A retries the load at approximately a 1% duty cycle.
FLTTIME: Connection for user-programming of the fault timeout period. An external capacitor connected from
FLTTIME to VIN establishes the timeout period to declare a fault condtion. This timeout protects against
indefinite current sourcing into a faulted load, and also provides a filter against nuisance trips from momentary
current spikes or surges. The TPS2393A defines a fault condition as voltage at the ISENS pin at or greater than
the 40-mV fault threshold. When a fault condition exists, the timer is active. The device manages fault timing
by charging the external capacitor to the 4-V fault threshold, then discharging it at approximately 1% the charge
rate to establish the duty cycle for retrying the load. Whenever the internal fault latch is set (timer expired), the
pass FET is rapidly turned off, and the FAULT output is asserted.
GATE: Gate drive for external Nchannel FET. When enabled, and the input supply is above the UVLO
threshold, the gate drive is enabled and the device begins charging an external capacitor connected to the
IRAMP pin. This pin voltage is used to develop the reference voltage at the non-inverting input of the internal
LCA. The inverting input is connected to the current sense node, ISENS. The LCA acts to slew the pass FET
gate to force the ISENS voltage to track the reference. The reference is internally clamped at 40 mV, so the
maximum current that can be sourced to the load is determined by the sense resistor value as IMAX
≤ 40
mV/RSENSE. Once the load voltage has ramped up to the input dc potential, and current demand drops off, the
LCA drives the GATE output to about 14 V to fully enhance the pass FET, completing the low-impedance supply
return path for the load.
INSA: Insertion detection input pin A. The INSA and INSB inputs work together to provide an insertion detection
function for TPS2393A applications. In order to turn on the FET gate drive (the GATE output), both INSA and
INSB must be pulled below the detection threshold, approximatey 1.4 V. Implementations using this feature
provide a mechanism for resistively pulling these pins to VIN potential (device ground), through the backplane
wiring. When used with slot connector pin staging this feature can keep the plug-in powered off during contact
bounce periods of the power pins. An on-chip pull-up is provided at each INSx pin; no additional pull-up is
needed to hold the pins high during the insertion and extraction processes. The insertion inputs are debounced
with a nominal 6.2-ms filter.
INSB: Insertion detection input pin B. See INSA description.
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