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參數(shù)資料
| 型號： | TPS2490DGSRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO10 |
| 封裝： | GREEN, PLASTIC, MSOP-10 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 534K |
| 代理商： | TPS2490DGSRG4 |
SLVS503C
– NOVEMBER 2003 – REVISED SEPTEMBER 2011
Faults and Backplane Voltage Droop
A hard short at the output of the TPS2490/91 during normal operation could result in activation of the enable or
UVLO circuit instead of the current limit if the input voltage droops sufficiently. The lower GATE drive in this
condition will cause a prolonged, larger over-current spike. This can be eliminated by filtering EN, or distributing
capacitance on the bus itself. Capacitance from adjacent plugged-in units may help with this as well.
Output Clamp Diode
Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during a
current limit. The OUT pin ratings can be maintained with a small diode, such as an S1B, across TPS2490/91
OUT to GND.
Gate Clamp Diode
The TPS2490/91 has a relatively well-regulated gate voltage of 12
–16 V, even with low supply voltages. A small
clamp Zener from gate to source of M1, such as a BZX84C7V5, is recommended if VGS of M1 is rated below this.
High Gate Capacitance Applications
Gate voltage overstress and abnormally large fault current spikes can be caused by large gate capacitance. An
external gate clamp Zener diode is recommended to assist the internal Zener if the total gate capacitance of M1
exceeds about 4000 pF. When gate capacitor dv/dt control is used, a 1-k
resistor in series with CG is
recommended. If the series R-C combination is used for MOSFETs with CISS less than 3000 pF, then a Zener is
not necessary.
Input Bypass
C1 should be present for control of external noise at VCC and as a low-impedance source for high-speed
circuits.
Output Short Circuit Measurements
Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads,
circuit layout and component selection, output shorting method, relative location of the short, and instrumentation
all contribute to obtaining different results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in the data sheet
—every setup differs.
Layout Considerations
Good layout practice places the power devices D1, RS, M1, and CO so power flows in a sequential fashion, and
preferably in a straight line. A ground plane under the power and the TPS2490/91 is desirable. The TPS2490/91
should be placed close to the sense resistor and the MOSFET; a Kelvin connection is recommended to achieve
accurate current sensing across RS. A low-impedance GND connection is required because the TPS2490/91 can
momentarily sink upwards of 100 mA from the gate of M1. The GATE amplifier has high bandwidth while active,
so keep the gate trace length short. The PROG, TIMER, and EN pins have high input impedances, therefore
keep their input leads short. Oversize power traces and power device connections to assure low voltage drop
and good thermal performance.
Copyright
2003–2011, Texas Instruments Incorporated
17
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