參數(shù)資料
型號： TPS3618-50DGKT
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
封裝： 3.05 X 4.98 MM, GREEN, PLASTIC, MSOP-8
文件頁數(shù)： 10/16頁
文件大小： 455K
代理商： TPS3618-50DGKT
www.ti.com
ELECTRICAL CHARACTERISTICS
SLVS339D – DECEMBER 2000 – REVISED DECEMBER 2006
1.65 V
≤ V
DD≤ 5.5 V, RLRESET = 1 M, CLRESET = 50 pF, over operating temperature range (TJ = –40°C to +85°C), unless
otherwise noted. Typical values are at T
J = +25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
Input supply range
1.65
5.5
V
VOUT = VDD
40
IDD
VDD supply current
A
VOUT = VBAT
40
VBAT
Battery supply range
1.5
5.5
V
VOUT = VDD
–0.1
0.1
IBAT
VBAT supply current
A
VOUT = VBAT
0.5
Slew rate at VDD or VBAT
1
V/
s
VI
Input volrage, any input
0
VDD + 0.3
V
VDD = 1.8 V, IOH = –400 A
VDD – 0.2
RESET
VDD = 3.3 V, IOH = –2 mA,
VDD – 0.4
VDD = 5 V, IOH = –3 mA
VOH
High-level output voltage
V
VDD = 1.8 V, IOH = –20 A
VDD – 0.3
PFO
VDD = 3.3 V, IOH = –80 A,
VDD – 0.4
VDD = 5 V, IOH = –120 A
VDD = 1.8 V, IOL = 400 A
0.2
VOL
Low-level output voltage
RESET PFO
V
VDD = 3.3 V, IOL = 2 mA,
0.4
VDD = 5 V, IOL = 3 mA
VBAT > 1.1 V, or VDD > 1.1 V,
VRES
Power-up reset voltage (1)
0.4
V
IOL = 20 A
IO = 8.5 mA,VDD = 1.8 V, VBAT = 0 V
VDD – 0.050
Normal mode
IO = 125 mA,VDD = 3.3 V, VBAT = 0 V
VDD – 0.150
VOUT
IO = 200 mA,VDD = 5 V, VBAT = 0 V
VDD – 0.200
V
IO = 0.5 mA,VBAT = 1.5 V, VDD = 0 V
VBAT – 0.200
Battery-backup mode
IO = 7.5 mA,VBAT = 3.3 V, VDD = 0 V
VBAT – 0.113
VDD to VOUT on-resistance
VDD = 5 V
0.6
1
RDS(on)
VBAT to VOUT on-resistance
VBAT = 3.3 V
8
15
IO
Continuous output current at VOUT
300
mA
VIT
TPS3617-50
4.46
4.55
V
Negative-going input
TA = –40°C to +85°C
threshold voltage (2)
VPFI
PFI
1.13
1.15
1.17
V
1.65 V < VIT < 2.5 V
20
VIT hysteresis
2.5 V < VIT < 3.5 V
40
VHYS
3.5 V < VIT < 5.5 V
60
mV
PFI hysteresis
12
VBSW hysteresis (3)
VDD = 1.8 V
55
VIH
WDI high-level input voltage
0.7 x VDD
VIL
WDI low-level input voltage
0.3 x VDD
IIH
WDI high-level input current (4)
WDI = VDD = 5 V
150
A
IIL
WDI low-level input current (4)
WDI = 0 V, VDD = 5 V
–150
A
WDI input transition rise and fall rate,
t/V
100
ns/V
II
PFI input current
PFI voltage < VDD
–25
25
nA
PFO = 0 V, VDD = 1.8 V
–0.3
IOS
PFO short-circuit current
PFO = 0 V, VDD = 3.3 V
–1.1
mA
PFO = 0 V, VDD = 5 V
–2.4
(1)
The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 s/V.
(2)
To ensure the best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1
F) should be placed near the supply terminals.
(3)
For VDD < 1.6 V, VOUT switches to VBAT regardless of VBAT.
(4)
For details on how to optimize current consumption when using WDI, refer to the Watchdog section of this data sheet.
3
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