參數(shù)資料
型號(hào): TPS3618-50DGKTG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
封裝: 3.05 X 4.98 MM, GREEN, PLASTIC, MSOP-8
文件頁(yè)數(shù): 2/16頁(yè)
文件大小: 455K
代理商: TPS3618-50DGKTG4
www.ti.com
DETAILED DESCRIPTION
BATTERY FRESHNESS SEAL (TPS3617 Only)
POWER-FAIL COMPARATOR (PFI AND PFO)
WATCHDOG
VIT
WDI
RESET
td
t(tout)
VOUT
td
Undefined
SLVS339D – DECEMBER 2000 – REVISED DECEMBER 2006
The battery freshness seal of the TPS3617 family disconnects the backup battery from the internal circuitry until
it is needed. This ensures that the backup battery connected to VBAT should be fresh when the final product is
put to use. The following steps explain how to enable the freshness seal mode:
1. Connect VBAT (VBAT > VBAT(min)).
2. Ground PFO.
3. Connect PFI to VDD (PFI = VDD).
4. Connect VDD to power supply (VDD > VIT) and keep connected for 5 ms < t < 35 ms.
The battery freshness seal mode is disabled by the positive-going edge of RESET when VDD is applied.
An additional comparator monitors voltages other than the nominal supply voltage. The power-fail-input (PFI)
can be compared with an internal voltage reference of 1.15 V. If the input voltage falls below the power-fail
threshold (V(PFI)) of 1.15 V typical, the power-fail output (PFO) goes low. If it goes above V(PFI) plus about 12-mV
hysteresis, the output returns to high. By connecting two external resistors it is possible to supervise any
voltages above V(PFI). The sum of both resistors should be about 1 M, to minimize power consumption and
also to ensure that the current in the PFI pin can be neglected compared with the current through the resistor
network. The tolerance of the external resistors should be not more than 1% to ensure minimal variation of the
sensed voltage. If the power-fail comparator is unused, connect PFI to ground and leave the PFO unconnected.
In a microprocessor- or DSP-based system, it is not only important to supervise the supply voltage, it is also
important to ensure correct program execution. The task of a watchdog is to ensure that the program is not
stalled in an indefinite loop. The microprocessor, microcontroller, or DSP has to toggle the watchdog input within
0.8 s typically, to avoid a timeout from occurring. Either a low-to-high or a high-to-low transition resets the
internal watchdog timer. If the input is unconnected, the watchdog is disabled and should be retriggered
internally. See Figure 13 for the watchdog timing diagram.
Figure 13. Watchdog Timing
10
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