參數(shù)資料
型號(hào): TPS3837K33MDBVREP
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
封裝: GREEN, PLASTIC, SOT-23, 5 PIN
文件頁(yè)數(shù): 1/16頁(yè)
文件大?。?/td> 499K
代理商: TPS3837K33MDBVREP
1
FEATURES
SUPPORTS DEFENSE, AEROSPACE,
3
2
4
5
1
CT
GND
MR
VDD
RESET
TPS3836, TPS3838
DBV PACKAGE
(TOP VIEW)
3
2
4
5
1
CT
GND
MR
VDD
RESET
TPS3837
DBV PACKAGE
(TOP VIEW)
APPLICATIONS
DESCRIPTION
www.ti.com.................................................................................................................................................... SGLS322D – MAY 2006 – REVISED NOVEMBER 2008
NANOPOWER SUPERVISORY CIRCUITS
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Supply Current of 220 nA (Typ)
Precision Supply Voltage Supervision Range:
1.8 V, 2.5 V, 3 V, 3.3 V
Power-On Reset Generator With Selectable
Delay Time of 10 ms or 200 ms
Push/Pull RESET Output (TPS3836), RESET
Output (TPS3837), or
Open-Drain RESET Output (TPS3838)
Manual Reset
5-Pin SOT-23 Package
AND MEDICAL APPLICATIONS
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range(1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Applications Using Automotive Low-Power
DSPs, Microcontrollers, or Microprocessors
Battery-Powered Equipment
Intelligent Instruments
Wireless Communication Systems
Automotive Systems
(1)
Custom temperature ranges available
The TPS3836, TPS3837, TPS3838 families of supervisory circuits provide circuit initialization and timing
supervision, primarily for digital signal processing (DSP) and processor-based systems.
During power on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the
supervisory circuit monitors VDD and keeps RESET output active as long as VDD remains below the threshold
voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system
reset. The delay time starts after VDD has risen above VIT.
When CT is connected to GND, a fixed delay time of typical 10 ms is asserted. When connected to VDD, the
delay time is typically 200 ms.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2006–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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