參數(shù)資料
型號(hào): TPS40071PWPR
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩(wěn)壓器
英文描述: 2 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16
封裝: GREEN, PLASTIC, HTSSOP-16
文件頁數(shù): 26/28頁
文件大小: 655K
代理商: TPS40071PWPR
APPLICATION INFORMATION
MINIMUM PULSE WIDTH
SLEW RATE LIMIT ON VDD
15
9
16
13
12
10
ILIM
HDRV
SW
LDRV
VDD
PGND
TPS40070
C
R
VIN
UDG05058
+
_
www.ti.com .................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009
The TPS40070 family of parts allows the user to construct synchronous voltage-mode buck converters with
inputs ranging from 4.5 V to 28 V and outputs as low as 700 mV. Predictive gate drive circuitry optimizes
switching delays for increased efficiency and improved converter output power capability. Voltage feed-forward is
employed to ease loop compensation and provide better line transient response.
A converter based on the TPS40070 operates as a single quadrant (source only) converter at all times. When
the rectifier FET is on and the controller senses that current is near zero in the inductor, the rectifier FET is
turned off, preventing the buildup of negative or reverse current in the inductor. This feature prevents the
converter from pulling energy from its output and forcing that energy onto its input.
Converters based on the TPS40071 operates as a two quadrant converter all the time (source and sink current).
This is the controller of choice for most applications.
The TPS4007x devices have limitations on the minimum pulse width that can be used to design a converter.
Reliable operation is guaranteed for nominal pulse widths of 250 ns and above. This places some restrictions on
the conversion ratio that can be achieved at a given switching frequency. Figure 2 shows minimum output
voltage for a given input voltage and frequency.
The regulator that supplies power for the drivers on the TPS40070/1 requires a limited rising slew rate on VDD
for proper operation if the input voltage is above 10 V. If the slew rate is too great, this regulator can over shoot
and damage to the part can occur. To ensure that the part operates properly, limit the slew rate to no more than
0.12 V/
s as the voltage at VDD crosses 8 V. If necessary, an R-C filter can be used on the VDD pin of the
device. Connect the resistor from the VDD pin to the input supply of the converter. Connect the capacitor from
the VDD pin to PGND. There should not be excessive (more than a 200-mV) voltage drop across the resistor in
normal operation. This places some constraints on
the R-C values that can be used. Figure 1 is a schematic
fragment that shows the connection of the R-C slew rate limit circuit. Equation 1 and Equation 2 give values for R
and C that limits the slew rate in the worst case condition.
Figure 1. Limiting the Slew Rate
Copyright 2003–2009, Texas Instruments Incorporated
7
Product Folder Link(s): TPS40070 TPS40071
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PDF描述
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