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| 型號： | TPS40077PWPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | GREEN, PLASTIC, HTSSOP-16 |
| 文件頁數(shù)： | 4/43頁 |
| 文件大?。?/td> | 847K |
| 代理商： | TPS40077PWPG4 |
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SLUS714D – JANUARY 2007 – REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com
Table 1. Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
The peak voltage on BOOST is equal to the SW node voltage plus the voltage present at DBP less the bootstrap
BOOST
14
I
diode drop. This drop can be 1.4 V for the internal bootstrap diode or 300 mV for an external Schottky diode. The
voltage differential between this pin and SW is the available drive voltage for the high-side FET.
Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the
COMP
8
O
FB pin to compensate the overall loop. The COMP pin is internally clamped to 3.4 V.
8-V reference used for the gate drive of the N-channel synchronous rectifier. This pin should be bypassed to
DBP
11
O
ground with a 1-
F ceramic capacitor.
Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal reference
FB
7
I
voltage, 0.7 V.
Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW
HDRV
13
O
(MOSFET off).
Short-circuit-protection programming pin. This pin is used to set the short circuit detection threshold. An internal
current sink from this pin to ground sets a voltage drop across an external resistor connected from this pin to VDD.
The voltage on this pin is compared to the voltage drop (VVDD – VSW) across the high side N-channel MOSFET
ILIM
16
I
during conduction. Just prior to the beginning of a switching cycle, this pin is pulled to approximately VDD/2 and
released when SW is within 2 V of VDD or after a timeout (the precondition time), whichever occurs first. Placing a
capacitor across the resistor from ILIM to VDD allows the ILIM threshold to decrease during the switch-on time,
effectively programming the ILIM blanking time. See Application Information.
A resistor connected from this pin to VIN programs the amount of feed-forward voltage. The current fed into this
KFF
1
I
pin is internally divided by 25 and used to control the slope of the PWM ramp and program undervoltage lockout.
Nominal voltage at this pin is maintained at 400 mV.
Gate drive for the N-channel synchronous rectifier. This pin switches from DBP (MOSFET on) to ground (MOSFET
LDRV
10
O
off). For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50 nC.
4.2-V reference used for internal device logic only. This pin should be bypassed by a 0.1-
F ceramic capacitor.
LVBP
3
O
External loads that are less than 1 mA and electrically quiet may be applied.
This is an open-drain output that pulls to ground when soft start is active, or when the FB pin is outside a ±10%
PGD
4
O
band around VREF.
Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of the
PGND
9
–
lower MOSFET(s).
RT
2
I
A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.
Signal ground reference for the device. Low-level quiet circuitry around the IC should connect to this pin. This pin
SGND
5
–
should be connected to the thermal pad under the IC, and that thermal pad should connect to the PGND pin. Do
not allow power currents to flow in the thermal pad or in the SGND part of the ground for best results.
Soft-start programming pin. A capacitor connected from this pin to GND programs the soft-start time. The
capacitor is charged with an internal current source of 12
A. The resulting voltage ramp on the SS pin is used as
a second noninverting input to the error amplifier. The voltage at this error amplifier input is approximately 1 V less
than that on the SS pin. Output voltage regulation is controlled by the SS voltage ramp until the voltage on the SS
SS
6
I
pin reaches the internal offset voltage of 1 V plus the internal reference voltage of 700 mV. If SS is pulled below
225 mV, the device goes into a shutdown state where the power FETSs are turned off and the prebias circuitry is
reset. If the programmed UVLO voltage is below 6 V, connect a 330-k
resistor in parallel with the SS capacitor.
Also provides timing for fault recovery attempts.
This pin is connected to the switched node of the converter. It is used for short-circuit sensing and gate-drive
SW
12
I
timing information and is the return for the high-side driver. A 1.5-
resistor is required in series with this pin for
protection against substrate current issues.
VDD
15
I
Supply voltage for the device.
12
Copyright 2007–2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS40077
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