參數(shù)資料
型號: TPS40200MDREPG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩(wěn)壓器
英文描述: SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, PDSO8
封裝: GREEN, PLASTIC, MS-012AA, SOIC-8
文件頁數(shù): 6/43頁
文件大?。?/td> 1069K
代理商: TPS40200MDREPG4
www.ti.com
MOSFET Gate Drive
Undervoltage Lockout (UVLO) Protection
8
5
+
1.3V
VDD
GND
200K
-
545k
RUN
TPS40200
+
36K
SGLS371 – JANUARY 2007
GENERAL INFORMATION (continued)
The output driver sinking current is approximately 200 mA and is designed to drive P-channel power FETs.
When the driver pulls the gate charge of the FET, it is controlling to –8 V, the drive current folds back to a low
level so that high power dissipation only occurs during the turnon period of the FET. This feature is particularly
valuable when turning on a FET at high input voltages, where leaving the gate drive current on would otherwise
cause unacceptable power dissipation.
UVLO protection ensures proper startup of the device only when the input voltage has exceeded minimum
operating voltage. Undervoltage protection incorporates hysteresis, which eliminates hiccup starting in cases
where input supply impedance is high.
Figure 28. Undervoltage Lockout
Undervoltage protection ensures proper startup of the device only when the input voltage has exceeded
minimum operating voltage. The UVLO level is measured at the VDD pin with respect to GND. Startup voltage is
typically 4.3 V, with approximately 200 mV of hysteresis. The part shuts off at a nominal 4.1 V. As shown in
Figure 28, when the input VDD voltage rises to 4.3 V , the 1.3-V comparator’s threshold voltage is exceeded and
a RUN signal occurs. Feedback from the output closes the switch and shunts the 200-k
resistor so that an
approximate 200-mV lower voltage, or 4.1 V, is required before the part shuts down.
14
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