參數(shù)資料
型號(hào): TPS5110PW
廠(chǎng)商: TEXAS INSTRUMENTS INC
元件分類(lèi): 穩(wěn)壓器
英文描述: 1.5 A SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, PDSO24
封裝: GREEN, PLASTIC, TSSOP-24
文件頁(yè)數(shù): 14/43頁(yè)
文件大?。?/td> 813K
代理商: TPS5110PW
TPS5110
SLVS025B APRIL 2002 REVISED JULY 2004
21
www.ti.com
APPLICATION INFORMATION
current protection (SBRC)
The current limit in TPS5110 is set using an internal current source and an external resistor (R13). The current
limit protection circuit compares the drain-to-source voltage of the high-side and low-side drivers with respect
to the set-point voltage. If the voltage up exceeds the limit during high-side conduction, the current-limit circuit
terminates the high-side driver pulse. If the set point voltage is exceeded during low-side conduction, the
low-side pulse is extended through the next cycle. Together this action has the effect of decreasing the output
voltage until the under voltage protection circuit is activated and the fault latch is set and both the high and
low-side MOSFET drivers are shut off. The equation below should be used for calculating the external resistor
value for current protection set point:
R
CL +
R
DS(on)
I
TRIP )
I
RIPPLE
2
13
106
where RCL is the external current limit resistor (R13); RDS(on) is the low-side MOSFET(Q02) on-time resistance.
ITRIP is the required current limit.
Example: RDS(on) = 25 m, ITRIP = 6 A, IRIPPLE = 1.93 A, therefore, RCL = 13.4 k.
It should be noted that RDS(on) of a FET is highly dependent on temperature, so to insure full output at maximum
operating temperature, the value of RDS(on) in the above equation should be adjusted. For maximum stability,
it is recommended that the high-side MOSFET(s) has same, or slightly higher RDS(on) than the low-side
MOSFET(s). If the low-side MOSFET(s) has a higher RDS(on), in certain low duty cycle applications it may be
possible for the device to regulate at an output current higher than that set by the above equation by increasing
the high side conduction time to compensate for the missed conduction cycle caused by the extension of the
previous low-side pulse.
timer latch
The TPS5110 includes fault latch function with a user adjustable timer to latch the MOSFET drivers in case of
a fault condition. When either the OVP or UVP comparator detect a fault condition, the timer starts to charge
FLT capacitor (C07), which is connected with FLT pin 10. The circuit is designed so that for any value of FLT
capacitor, the under-voltage latch time t(uvplatch) is about 50 times larger than the over-voltage latch time
t(ovplatch). The equations needed to calculate the required value of the FLT capacitor for the desired over and
under-voltage latch delay times are:
C
LAT +
2.3
10*6
t
(uvplatch)
1.185
and
C
LAT +
125
10*6
t
(ovplatch)
1.185
where CLAT is the external capacitor, t(uvplatch) is the time from UVP detection to latch. t(ovplatch) is the time from
OVP detection to latch.
For the EVM, t(uvplatch) = 5 ms and t(ovplatch) = 0.1 ms, so CLAT = 0.01 F
If the voltage on the FLT pin reaches 1.185 V, the fault latch is set, and the MOSFET drivers are set as follows:
under-voltage protection
The under-voltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the
voltage at either pin falls below 65% of the 0.85-V reference, the timer begins to charge the FLT capacitor. If
the fault condition persists beyond the time t(uvplatch), the fault latch is set and both the high side and low-side
drivers, and LDO regulator drivers are forced OFF.
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