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| 型號(hào)： | TPS51461RGET |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PQCC24 |
| 封裝： | 4 X 4 MM, GREEN, PLASTIC, QFN-24 |
| 文件頁(yè)數(shù)： | 27/31頁(yè) |
| 文件大?。?/td> | 1627K |
| 代理商： | TPS51461RGET |
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www.ti.com
SLUSAD9 – DECEMBER 2010
ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VVIN = 5.0 V, VV5DRV = VV5FILT = 5 V, MODE = OPEN, PGND = GND (unless
otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
PROTECTION: OVP, UVP, PGOOD, and THERMAL SHUTDOWN
PGOOD deassert to lower
VPGDLL
Measured at the VOUT pin w/r/t VSLEW
82%
84%
86%
(PGOOD
→ Low)
VPGHYSHL
PGOOD high hysteresis
8%
PGOOD de-assert to higher
VPGDLH
Measured at the VOUT pin w/r/t VSLEW
114%
116%
118%
(PGOOD
→ Low)
VPGHYSHH
PGOOD high hysteresis
-8%
Minimum VIN voltage for valid
Measured at the VIN pin with a 2-mA sink current on PGOOD
VINMINPG
1.0
1.3
1.5
V
PGOOD
pin
VOVP
OVP threshold
Measured at the VOUT pin w/r/t VSLEW
118%
120%
122%
Measured at the VOUT pin w/r/t VSLEW, device latches OFF,
VUVP
UVP threshold
66%
68%
70%
begins soft-stop
THSD
Thermal shutdown (2)
Latch off controller, attempt soft-stop.
130
°C
THSD(hys)
Thermal Shutdown hysteresis(2)
Controller re-starts after temperature has dropped
10
°C
TIMERS: ON-TIME, MINIMUM OFF TIME, SS, AND I/O TIMINGS
VVIN = 5 V, VVOUT = 0.8 V, fSW = 667 kHz, fixed VID mode
240
ns
tONESHOTC
PWM one-shot(2)
VVIN = 5 V, VVOUT = 0.8 V, fSW = 1 MHz, fixed VID mode
160
ns
VVIN = 5 V, VVOUT = 0.8 V, fSW = 1 MHz, DRVL on,
tMIN(off)
Minimum OFF time
357
ns
SW = PGND, VVOUT < VSLEW
PGOOD startup delay time (excl.
Delay starts from VOUT = VID code 00 and excludes SLEW
tPGDDLY
3
ms
SLEW ramp up time)
ramp up time
tPGDPDLYH
PGOOD high propagation delay time
50 mV over drive, rising edge
0.8
1
1.2
ms
tPGDPDLYL
PGOOD low propagation delay time
50 mV over drive, falling edge
10
s
tOVPDLY
OVP delay time
Time from the VOUT pin out of +20% of VSLEW to OVP fault
0.2
s
Undervoltage fault enable delay (excl.
Time from (VOUT = VID code 00) going high to undervoltage
tUVDLYEN
3
ms
SLEW ramp up time)
fault is ready
tUVPDLY
UVP delay time
Time from the VOUT pin out of –30% of VSLEW to UVP fault
8.5
s
ISLEW
Soft-start and voltage transition
CSS = 10 nF assuming voltage slew rate of 1 mV/s
9
10
11
A
LOGIC PINS: I/O VOLTAGE AND CURRENT
VPGDPD
PGOOD pull down voltage
PGOOD low impedance, ISINK = 4 mA, VVIN = VV5FILT = 4.5 V
0.3
V
IPGDLKG
PGOOD leakage current
PGOOD high impedance, forced to 5.5 V
–1
0
1
A
VENH
EN logic high
EN, VCCP logic
0.8
V
VENL
EN logic low
EN, VCCP logic
0.3
V
IEN
EN input current
1
A
VVIDH
VID logic high
VID0, VID1
0.8
V
VVIDL
VID logic low
VID0, VID1
0.3
V
IVID
VID input current
1
A
MODE 1
0.08
0.13
0.18
MODE 3
0.37
0.42
0.47
VMODETH
MODE threshold voltage(3)
MODE 4
0.55
0.60
0.65
V
MODE 5
0.83
0.88
0.93
MODE 7
1.75
1.80
1.85
IMODE
MODE current
15
A
RPD
VID pull-down resistance
10
k
Ω
(2)
Ensured by design, not production tested.
(3)
See Table 3 for descriptions of MODE parameters.
Copyright 2010, Texas Instruments Incorporated
5
Product Folder Link(s): TPS51461
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