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0 +
1
2p
ESR
Co
v
sw
3
(20)
Thermal Design
W
DSRC + VVLDOIN * VVLDO
I
VLDO
(21)
V
PKG +
T
J(max) * TA(max)
q
JA
(22)
SLVS735A – FEBRUARY 2007 – REVISED APRIL 2007
APPLICATION INFORMATION (continued)
The VOSW voltage is compared with the internal reference voltage from the divider resistors. The PWM
comparator determines the timing to turn on the top MOSFET. The gain and speed of the comparator is high
enough to keep the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The
DC output voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage
increases.
To ensure loop stability, the 0dB frequency, f0, defined below, should be lower than 1/3 of the switching
frequency.
Because f0 is determined solely by the output capacitor’s characteristics, the loop stability of D-CAP Mode is
determined by the capacitor’s chemistry. For example, specialty polymer capacitors (SP-CAP) have Co in the
order of several-hundred
F and ESR values in the range of 10 m. These will make f
0 approximately 100 kHz
or less, and the loop will be stable. However, ceramic capacitors have f0 at more than 700 kHz, which is not
suitable for this mode.
D-CAP mode provides many advantages such as ease-of-use, minimum external component count and
extremely short response time. However, because it does not employ an error amplifier in the loop, a sufficient
amount of feedback signal must be provided by the external circuit to reduce jitter level. A good layout which
follows the layout considerations in this data sheet also can reduce the jitter level.
Components selection is much simpler in D-CAP mode.
1. Choose inductor.
This section is the same as the current mode. Refer to the instructions in the
Current Mode Section.
2. Choose output capacitor(s).
Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended.
The primary power dissipation of TPS51511 is generated from the LDO. The potential difference between
VLDOIN and VLDO times LDO current gives the power dissipation, WDSRC,
Another power consideration is the current used for internal control circuitry from the V5IN supply. V5IN supports
both the internal circuitry and the external MOSFET drive current.
These powers need to be effectively dissipated from the package. Maximum power dissipation allowed to the
package is calculated by,
Where:
TJ(max) is 125°C
TA(max) is the maximum ambient temperature in the system
θ
JA is the thermal resistance from the silicon junction to the ambient
This thermal resistance strongly depends on the board layout. TPS51511 is assembled in a thermally enhanced
PowerPAD package that has an exposed die pad underneath the body. For maximum thermal performance, this
die pad must be attached to a ground trace via a thermal land on the PCB. This ground trace acts as a heat
sink. The typical thermal resistance, 53.3
°C/W, is achieved based on a 3,05 mm × 2,05 mm thermal land with 6
vias without air flow. It can be improved by using a larger thermal land and/or increasing the number of vias.
Further information about PowerPAD and its recommended board layout is described in a Texas Instruments
document, SLMA002. This document is available at www.TI.com. 19