參數(shù)資料
型號: TPS53314RGFT
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩(wěn)壓器
英文描述: SWITCHING REGULATOR, 1070 kHz SWITCHING FREQ-MAX, PQCC40
封裝: 5 X 7 MM, GREEN, PLASTIC, VQFN-40
文件頁數(shù): 14/29頁
文件大小: 800K
代理商: TPS53314RGFT
( )
(
)
-
=
IN
OUT
OUT LL
SW
IN
V
1
I
2
L
f
V
(
)
( )
=
W
m
TRIP
V
mV
R
k
I
A
SLUSAK3
– MAY 2011
Auto-Skip Eco-mode
Light Load Operation
While the MODE pin is pulled low via RMODE, the TPS53314 automatically reduces the switching frequency at
light-load conditions to maintain high efficiency. Detailed operation is described as follows. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that
its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The synchronous MOSFET is turned off when this zero inductor current is detected. As the
load current further decreases, the converter runs into discontinuous conduction mode (DCM). The on-time is
maintained as it was in the continuous conduction mode so that it takes longer time to discharge the output
capacitor with smaller load current to the level of the reference voltage. The transition point to the light-load
operation IOUT(LL) (i.e., the threshold between continuous and discontinuous conduction mode) can be calculated
as shown in Equation 3.
where
SW is the PWM switching frequency
(3)
Switching frequency versus output current in the light load condition is a function of L, VIN and VOUT, but it
decreases almost proportionally to the output current from the IOUT(LL) given in Equation 3. For example, it is 60
kHz at IOUT(LL)/5 if the frequency setting is 300 kHz.
Adaptive Zero Crossing
The TPS53314 has an adaptive zero crossing circuit which performs optimization of the zero inductor current
detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and
compensates inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit. It
prevents SW-node swing-up caused by postponed detection and minimizes diode conduction period caused by
premature detection. As a result, better light-load efficiency is delivered.
Forced Continuous Conduction Mode
When the MODE pin is tied to PGOOD through a resistor, the controller keeps continuous conduction mode
(CCM) during light-load conditions. In this mode, the switching frequency is maintained over the entire load range
which is suitable for applications needing tight control of the switching frequency at a cost of lower efficiency.
Power Good
The TPS53314 has powergood output that indicates high when switcher output is within the target. The
powergood function is activated after soft-start has finished. If the output voltage becomes within +10% or
–5% of
the target value, internal comparators detect the powergood state and the powergood signal becomes high after
a 1-ms internal delay. If the output voltage goes outside of +15% or
–10% of the target value, the power-good
signal becomes low after two microsecond (2-
μs) internal delay. The powergood output is an open drain output
and must be pulled up externally.
In order for the PGOOD logic to be valid, the VDD input must be higher than 1 V. To avoid invalid PGOOD logic
before the TPS53314 is powered up, it is recommended the PGOOD be pull to VREG (either directly or through
a resistor divider) because VREG remains low when the device is off.
Current Sense and Overcurrent Protection
TPS53314 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state
and the controller maintains the OFF state during the period in that the inductor current is larger than the
overcurrent trip level. In order to provide both good accuracy and cost effective solution, TPS53314 supports
temperature compensated MOSFET RDS(on) sensing. The TRIP pin should be connected to GND through the trip
voltage setting resistor, RTRIP. The TRIP pin sources ITRIP current, which is 10 μA typically at room temperature,
and the trip level is set to the OCL trip voltage VTRIP as shown in Equation 4.
(4)
Copyright
2011, Texas Instruments Incorporated
21
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