參數(shù)資料
型號: TPS53353DQPT
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩(wěn)壓器
英文描述: SWITCHING REGULATOR, PDSO22
封裝: 5 X 6 MM, ROHS COMPLIANT, PLASTIC, SON-22
文件頁數(shù): 15/25頁
文件大?。?/td> 556K
代理商: TPS53353DQPT
To GND Plane
Bottom side
components and trace
Bottom side
component
and trace
GND shape
Keep VFB trace short and
away from noisy signals
VIN shape
VOUT shape
LL shape
R
F
T
R
IP
M
O
D
E
V
D
VREG
PGOOD
EN
VFB
VOUT
GND
Bottom side
components and trace
VBST
UDG-11166
SLUSAK2
– AUGUST 2011
LAYOUT CONSIDERATIONS
Certain points must be considered before starting a layout work using the TPS53353.
The power components (including input/output capacitors, inductor and TPS53353) should be placed on one
side of the PCB (solder side). At least one inner plane should be inserted, connected to ground, in order to
shield and isolate the small signal traces from noisy power lines.
All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE and RF should be placed
away from high-voltage switching nodes such as LL, VBST to avoid coupling. Use internal layer(s) as ground
plane(s) and shield feedback trace from power traces and components.
Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input AC
current loop.
Because the TPS53353 controls output voltage referring to voltage across VOUT capacitor, the top-side
resistor of the voltage divider should be connected to the positive node of the VOUT capacitor. The GND of
the bottom side resistor should be connected to the GND pad of the device. The trace from these resistors to
the VFB pin should be short and thin.
Place the frequency setting resistor (RF), OCP setting resistor (RTRIP) and mode setting resistor (RMODE) as
close to the device as possible. Use the common GND via to connect them to GND plane if applicable.
Place the VDD and VREG decoupling capacitors as close to the device as possible. Ensure to provide GND
vias for each decoupling capacitor and make the loop as small as possible.
The PCB trace defined as switch node, which connects the LL pins and high-voltage side of the inductor,
should be as short and wide as possible.
Connect the ripple injection VOUT signal (VOUT side of the C1 capacitor in Figure 2) from the terminal of
ceramic output capacitor. The AC coupling capacitor (C2 in Figure 2) should be placed near the device, and
R7 and C1 can be placed near the power stage.
Use separated vias or trace to connect LL node to snubber, boot strap capacitor and ripple injection
capacitor. Do not combine these connections.
Figure 39. Layout Recommendation
22
Copyright
2011, Texas Instruments Incorporated
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