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參數(shù)資料
| 型號： | TPS5420MDREP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 5.2 A SWITCHING REGULATOR, 600 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | GREEN, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 7/23頁 |
| 文件大?。?/td> | 658K |
| 代理商： | TPS5420MDREP |
www.ti.com
ADVANCED INFORMATION
Output Voltage Limitations
V
OUTMAX + 0.87
V
INMIN * IOMAX
0.230 ) VD * IOMAX
R
L * VD
(13)
V
OUTMIN + 0.12
V
INMAX * IOMIN
0.110 ) VD * IOMIN
R
L * VD
(14)
Internal Compensation Network
H(s) +
1 )
s
2p
Fz1
1 )
s
2p
Fz2
s
2p
Fp0
1 )
s
2p
Fp1
1 )
s
2p
Fp2
1 )
s
2p
Fp3
(15)
SLVS717 – DECEMBER 2006
Due to the internal design of the TPS5420, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:
Where:
VINMIN = Minimum input voltage
IOMAX = Maximum load current
VD = Catch diode forward voltage
RL = Output inductor series resistance
This equation assumes maximum on-resistance for the internal high-side FET.
The lower limit is constrained by the minimum controllable on time, which may be as high as 200 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by:
Where:
VINMAX = Maximum input voltage
IOMIN = Minimum load current
VD = Catch diode forward voltage
RL = Output inductor series resistance
This equation assumes nominal on resistance for the high-side FET and accounts for worst-case variation of
operating frequency set point. Any design operating near the operational limits of the device should be checked
to ensure proper functionality.
The design equations given in the example circuit can be used to generate circuits using the TPS5420. These
designs are based on certain assumptions, and always select output capacitors within a limited range of ESR
values. If a different capacitor type is desired, it may be possible to fit one to the internal compensation of the
TPS5420. Equation 15 gives the nominal frequency response of the internal voltage-mode type III compensation
network:
Where:
Fp0 = 2165 Hz, Fz1 = 2170 Hz, Fz2 = 2590 Hz
Fp1 = 24 kHz, Fp2 = 54 kHz, Fp3 = 440 kHz
Fp3 represents the non-ideal parasitics effect.
Using this information, along with the desired output voltage, feed-forward gain, and output filter characteristics,
the closed-loop transfer function can be derived.
15
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