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參數(shù)資料
| 型號(hào)： | TPS54240QDGQRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2.5 A SWITCHING REGULATOR, 2500 kHz SWITCHING FREQ-MAX, PDSO10 |
| 封裝： | GREEN, PLASTIC, MSOP-10 |
| 文件頁數(shù)： | 16/48頁 |
| 文件大?。?/td> | 1447K |
| 代理商： | TPS54240QDGQRQ1 |
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RT/CLK
TPS54240
Clock
Source
PLL
Rfset
10pF
4kW
50 W
EXT
SLVSAQ4A
– DECEMBER 2010 – REVISED APRIL 2011
DETAILED DESCRIPTION (continued)
How to Interface to RT/CLK Pin
The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the
synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in
Figure 42. The square wave amplitude must transition lower than 0.5V and higher than 2.2V on the RT/CLK pin
and have an on time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range
is 300 kHz to 2200 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal.
The external synchronization circuit should be designed in such a way that the device will have the default
frequency set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. It is
recommended to use a frequency set resistor connected as shown in Figure 42 through a 50
resistor to
ground. The resistor should set the switching frequency close to the external CLK frequency. It is recommended
to ac couple the synchronization signal through a 10 pF ceramic capacitor to RT/CLK pin and a 4k
series
resistor. The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock
and in applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the
CLK threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5V voltage source
is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Since
there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with the
external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or
decrease the switching frequency until the PLL locks onto the CLK frequency within 100 microseconds.
When the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK
frequency to 150 kHz, then reapply the 0.5V voltage and the resistor will then set the switching frequency. The
switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The
device implements a digital frequency shift to enable synchronizing to an external clock during normal startup
and fault conditions. Figure 43, Figure 44 and Figure 45 show the device synchronized to an external system
clock in continuous conduction mode (ccm) discontinuous conduction (dcm) and pulse skip mode (psm).
Figure 42. Synchronizing to a System Clock
Copyright
2010–2011, Texas Instruments Incorporated
23
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| TPS54240QDRCRQ1 | 功能描述:Buck, Split Rail Switching Regulator IC Positive Adjustable 0.8V 1 Output 2.5A 10-VFDFN Exposed Pad 制造商:texas instruments 系列:汽車級(jí)，AEC-Q100，SWIFT?，Eco-Mode? 包裝:剪切帶（CT） 零件狀態(tài):有效 功能:降壓 輸出配置:正 拓?fù)?降壓，分離軌 輸出類型:可調(diào)式 輸出數(shù):1 電壓 - 輸入（最小值）:3.5V 電壓 - 輸入（最大值）:42V 電壓 - 輸出（最小值/固定）:0.8V 電壓 - 輸出（最大值）:39V 電流 - 輸出:2.5A 頻率 - 開關(guān):100kHz ~ 2.5MHz 同步整流器:無 工作溫度:-40°C ~ 125°C（TA） 安裝類型:表面貼裝 封裝/外殼:10-VFDFN 裸露焊盤 供應(yīng)商器件封裝:10-VSON（3x3） 標(biāo)準(zhǔn)包裝:1 |
| TPS54260 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.5V to 60V INPUT, 2.5A, STEP DOWN CONVERTER WITH ECO-MODE? |
| TPS54260_1 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.5V to 60V INPUT, 2.5A, STEP DOWN CONVERTER WITH ECO-MODE? |
| TPS54260_2 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.5V to 60V INPUT, 2.5A, STEP DOWN CONVERTER WITH ECO-MODE? |
| TPS54260DGQ | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 3.5-60V 2.5A 2.5MHz Step Down Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
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