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Stabilizing the Control Loop
C9 +
6.8 ms
R1
(11)
C10 +
7.5 ms
R3
(12)
Layout Considerations
THERMAL INFORMATION
P
DMAX +
T
JMAX *
T
A
R
qJA
(13)
TPS65130, TPS65131
SLVS493B – MARCH 2004 – REVISED SEPTEMBER 2004
Feedback Divider
To speed up the control loop, feedforward capacitors are recommended in the feedback divider, parallel to R1
(boost converter) and R3 (inverting converter). Equation 11 shows how to calculate the appropriate value for the
boost converter, and Equation 12 for the inverting converter.
To avoid coupling noise into the control loop from the feedforward capacitors, the feedforward effect can be
bandwith-limited by adding a series resistor. Any value between 10 k
and 100 k is suitable. The higher the
resistance, the lower the noise coupled into the control loop system.
Compensation Capacitors
The control loops of both converters are completely compensated internally. The complex internal input voltage
output voltage, and input-current feedforward system has built-in error correction which requires external
capacitors. A 10-nF capacitor at CP of the boost converter and a 4.7-nF capacitor at CN of the inverting
converter is recommended.
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current paths and for the power ground
tracks. The input capacitors, output capacitors, the inductors, and the rectifying diodes should be placed as close
as possible to the IC to keep parasitic inductances low. Use a common ground node for power ground and a
different node for control grounds to minimize the effects of ground noise. Connect these ground nodes at any
place close to one of the ground pins of the IC.
The feedback dividers should be placed as close as possible to the control ground pin (boost converter) or the
VREF pin (inverting converter) of the IC. To lay out the control ground, it is recommended to use short traces as
well, seperated from the power ground traces. This avoids ground shift problems, which can occur due to
superimposition of power ground current and control ground current.
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues, such as thermal coupling, airflow, added
heatsinks
and
convection
surfaces,
and
the
presence
of
heat-generating
components
affect
the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance follow.
Improving the power dissipation capability of the PCB design
Improving the thermal coupling of the component to the PCB
Introducing airflow to the system
The maximum recommended junction temperature (TJ) of the TPS65130/1 devices is 125°C. The thermal
resistance of the 24-pin QFN, 4x4-mm package (RGE) is RθJA = 37.8°C/W. Specified regulator operation is
ensured to a maximum ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about
1058 mW. More power can be dissipated if the maximum ambient temperature of the application is lower.
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