參數(shù)資料
型號： TPS65150PWPR
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 3-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24
封裝： GREEN, PLASTIC, HTSSOP-24
文件頁數(shù)： 28/32頁
文件大小： 1412K
代理商： TPS65150PWPR
www.ti.com
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
FB
DLY1
DLY2
VIN
SW
PGND
SUP
VCOM
IN
FBP
FDLY
GD
COMP
FBN
REF
GND
DRVN
DRVP
CPI
VGH
ADJ
CTRL
Thermal
PowerP
AD*
1
2
3
4
5
6
18
17
16
15
14
13
7
8
9
10 11 12
19
20
21
22
23
24
Exposed
Thermal Die*
COMP
GD
FDLY
FB
DLY1
DLY2
VIN
SW
PGND
SUP
VGH
ADJ
CTRL
FBP
IN
VCOM
FBN
REF
GND
DR
VN
DR
VP
CPI
TPS65150
SLVS576 – SEPTEMBER 2005
TSSOP-24 Package
QFN-24 Package
Top View
* The thermal die (PowerPADTM) is connected to GND.
TERMINAL FUNCTIONS
TERMINAL
NO.
I/O
DESCRIPTION
NAME
QFN
TSSOP
Gate voltage shaping circuit. Connecting a capacitor to this pin sets the fall time of the
ADJ
17
14
I/O
positive gate voltage (VGH).
This is the compensation pin for the main boost converter. A small capacitor and if required
COMP
1
22
O
a series resistor is connected to this pin.
CPI
19
16
I
Input of the VGH isolation switch and gate voltage shaping circuit.
Control signal for the gate voltage shaping signal. Apply the control signal for the gate
voltage control. Usually the timing controller of the LCD panel generates this signal. If this
CTRL
16
13
I
function is not required, this pin needs to be connected to VIN. By doing this, the internal
switch between CPI and VGH provides isolation for the positive charge pump output VGH.
DLY2 sets the delay time for VGH to come up.
Power-on sequencing adjust. Connecting a capacitor from this pin to GND allows to set the
DLY1
5
2
I/O
delay time between the boost converter output Vs and the negative charge pump VGL
during startup.
Power-on sequencing adjust. Connecting a capacitor from this pin to GND allows to set the
delay time between the negative charge pump VGL and the positive charge pump during
DLY2
6
3
I/O
startup. Note that Q5 in the Gate Voltage Shaping block only turns on when the positive
charge pump (FBP) is within regulation. (This provides input to output isolation of VGH).
DRVN
21
18
I/O
Charge pump driver to generate the negative voltage VGL.
DRVP
20
17
I/O
Charge pump driver to generate the positive output voltage VGH.
FB
4
1
I
Feedback of the main boost converter generating Vsource (Vs).
FBN
24
21
I
Feedback pin of the negative charge pump VGL.
FBP
15
12
I
Feedback pin of the positive charge pump.
Fault delay. Connecting a capacitor from this pin to Vin allows to set the delay time from
the point when one of the outputs (VS, VGH, VGL) drops below its power good threshold
FDLY
3
24
I/O
until the devices enters the shutdown latch. To re-start the device the input voltage has to
be cycled to GND. This feature can be disabled by connecting the FDLY pin to Vin.
Active low open drain output. This output is latched low when the boost converter Vs is in
GD
2
23
I
regulation. This signal can be used to drive an external MOSFET to provide isolation for Vs.
GND
22
19
Analog ground
5
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