2
12
M
ps
fc Vo Co
R
g
Vref gm
p ×
×
=
×
SLVSAA4B – JUNE 2010 – REVISED JANUARY 2011
www.ti.com
Compensation
A type-II compensation circuit is adequate for the converter to have a phase margin between 60 and 90 degrees.
The following equations show the procedure of designing a peak current mode control dc/dc converter.
The compensation design takes the following steps:
1. Set up the anticipated cross-over frequency. In this example, the anticipated cross-over frequency (fc) is 65
kHz. The power stage gain (gmPS ) is 10 A/V and the GM amplifier gain (gM ) is 130 A/V.
(21)
2. Place compensation zero at low frequency to boost the phase margin at the crossover frequency. From the
procedures above, the compensation network includes a 20-k
resistor (R12) and a 4700-pF capacitor (C1).
3. An additional pole can be added to attenuate high frequency noise.
From the procedures above, the compensation network includes a 20-k
resistor (R12) and a 4700-pF capacitor
(C14).
3.3-V and 6.5-V LDO Regulators
The following ceramic capacitor (X7R/X5R) should be connected as close as possible to the described pins:
10 F for V7V pin 28
3.3 F for V3V pin 29
Layout Recommendation
Layout is a critical portion of PMIC designs.
Place VOUT, and LX on the top layer and an inner power plane for VIN.
Fit also on the top layer connections for the remaining pins of the PMIC and a large top side area filled with
ground.
The top layer ground area sould be connected to the internal ground layer(s) using vias at the input bypass
capacitor, the output filter cpacitor and directly under the TPS65251 device to provide a thermal path from the
Powerpad land to ground.
The AGND pin should be tied directly to the power pad under the IC and the power pad.
For operation at full rated load, the top side ground area together with the internal ground plane, must provide
adequate heat dissipating area.
There are several signals paths that conduct fast changing currents or voltages that can interact with stray
inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help
eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass
capacitor connections, the VIN pins, and the ground connections. Since the LX connection is the switching
node, the output inductor should be located close to the LX pins, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling.
The output filter capacitor ground should use the same power ground trace as the VIN input bypass capacitor.
Try to minimize this conductor length while maintaining adequate width.
The compensation should be as close as possible to the COMP pins. The COMP and OSC pins are sensitive
to noise so the components associated to these pins should be located as close as possible to the IC and
routed with minimal lengths of trace.
24
Copyright 2010–2011, Texas Instruments Incorporated