參數(shù)資料
型號: TQ2061
廠商: TriQuint Semiconductor,Inc.
英文描述: High-Frequency Clock Generator
中文描述: 高頻時鐘發(fā)生器
文件頁數(shù): 4/6頁
文件大?。?/td> 191K
代理商: TQ2061
TQ2061
4
For additional information and latest specifications, see our website:
www.triquint.com
Table 5. AC Characteristics (V
DD
= +5 V
+ 5%, T
A
= 0
°
C to +70
°
C)
Symbol
Input Clock (REFCLK)
Test Conditions (Figure 5)
Min
Typ
Max
Unit
t
CPWH
t
CPWL
t
IR
CLK pulse width HIGH
CLK pulse width LOW
Input rise time (0.8 V – 2.0 V)
Figure 5
Figure 5
4
4
2.0
ns
ns
ns
Symbol
Output Clock (Q, QN)
Test Conditions (Figures 4 & 5)
1
Min
Typ
Max
Unit
t
OR,
t
OF
t
CYC
t
JP2
t
SYNC3
Rise/fall time (20% – 80%)
Duty-cycle
Period-to-Period Jitter
Synchronization Time
Figure 5
Figure 5
100
45
220
50
25
10
350
55
70
500
ps
%
ps
μ
s
Notes: 1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V).
2. Jitter specification is peak to peak. Period-to-Period jitter is the jitter on the output with respect to the output's previous crossing.
3. t
SYNC
is the time required for the PLL to synchronize and assumes the presence of a CLK signal.
Figure 5. REFCLK and Q–QN Timing
Figure 4. PECL Test Load
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