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參數(shù)資料
| 型號： | TQ8004 |
| 英文描述： | Interface IC |
| 中文描述： | 接口IC |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 1218K |
| 代理商： | TQ8004 |
TQ8004
2
For additional information and latest specifications, see our website:
www.triquint.com
Circuit Description
Data inputs
The 4 input channels are differential PECL compatible,
referenced to VDD = 3.3V power supply (LVPECL). All
LVPECL inputs have on-chip 50 Ohm termination to
VTT.
For AC coupled designs an internal bias generator can
be used to supply the VTT voltage. An on-chip voltage
divider generates the VTT voltage at VDD-1.3V with an
impedance of 800 Ohms. Due to the high impedance of
the internal VTT source it is suited only for AC coupled
input schemes.
For DC coupled designs VTT needs to be externally
supplied, nominally at VDD-2.0V for LVPECL systems.
Note that the external source needs to be able to sink
current.
If any inputs are unused, terminate one side of any
unused input pair to GND through a 500 Ohm or
smaller resistor. This will prevent unwanted
oscillations.
Data outputs
The 4 output channels are differential PECL and are
designed to be terminated through 50 Ohm to VDD-
2.0V. Unused outputs can be left unterminated.
Control inputs
The control inputs are TTL compatible. Unconnected
inputs will default to a logic HI level.
Switch configuration
The switch is configured by programming each output
to a specific input. Each of the 4 output channels have
two sets of program store latches. The first, or
program latch, stores a new input configuration prior
to application to the switch core. The second, or
configuration latch, stores the current input
configuration which is applied to the switch core. The
use of two sets of program storage latches allows for a
new set of input configurations to be loaded
simultaneously without disturbing the existing
configuration.
The address of the desired output is applied to
OADD(0:1). The input address is applied to IADD(0:1).
The input address defines which input port connects to
the selected output port. The new configuration is
loaded into the program latches by asserting the LOAD
signal high and is latched when LOAD is de-asserted.
The process is repeated for each new output port
configuration. Only the output ports which are to
receive a new input port configuration need to be
programmed in this manner. The new configurations
are not applied to the switch core at this time.
After all of the new configurations have been loaded
into the program latches, the CONFIGURE input is
asserted high and the data in the program latches is
loaded into the configuration latches. The data is
latched when CONFIGURE is de-asserted. Data integrity
is maintained on output ports not receiving a new
configuration
The switch core receives the new configuration
immediately following the assertion of CONFIGURE.
The integrity of the data on any re-configured output
port is unknown for a period
t
dcf
from the time
CONFIGURE is asserted.
The LOAD and CONFIGURE inputs can be asserted
simultaneously. In this mode, the new configuration
will be applied to the switch when LOAD is asserted.
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