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參數(shù)資料
| 型號： | TRF3750IRGPRG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 16/37頁 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 20-QFN |
| 標準包裝： | 1,000 |
| 類型： | PLL 頻率合成器 |
| PLL： | 無 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 20-QFN 裸露焊盤（4x4） |
| 包裝： | 帶卷 (TR) |
| 配用： | TRF3750T-1900EVM-ND - TRF3750T-1900EVM TRF3750Q1900EVM-ND - TRF3750Q1900EVM 296-20836-ND - EVALUATION MOD FOR CDCM7005-QFN 296-20835-ND - EVALUATION MOD FOR CDCM7005-BGA 296-20834-ND - EVALUATION MOD FOR CDC7005-QFN |
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TRF3750
SLWS146B MARCH 2004 REVISED AUGUST 2007
www.ti.com
23
Reserved Bits
Bits DB22DB23 of the N counter latch are reserved and can be treated as don’t cares by the user.
Function Latch
Table 9 depicts the function latch. By selecting (0,1) for the control bits DB0 and DB1, the function latch is
selected.
Table 9. Function Latch
Prescaler
Value
Power
Down
2
Current
Setting 2
Current
Setting 1
Timer Counter
Control
Fasklock
Mode
Fasklock
Enable
CP
Tri
State
Reserved
MUXOUT
Control
Power
Down
1
Counter
Reset
Control
Bits
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11
DB10
DB9
DB8
DB7
DB6
DB5 DB4
DB3
DB2
DB1
DB0
P2
P1
PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1
F5
F4
F3
M3
M2
M1
PD1
F1
C2(1) C1(0)
X
Counter Reset Bit
When this bit is set to 1, all the counters in the PLL are reset. This includes the R, A, and B counters. In a typical
application, this bit should be set to 0.
Power Down
The complete power down functionality of the TRF3750 is controlled in software by the two bits DB3 and DB21
in the function latch and in hardware by the external pin CE (pin 10). When the TRF3750 enters the power down
state, the power consumption is lowered, the charge pump is 3-stated, but the registers are still operational
enabling programming of the device. The hardware power down (CE set to 0) is immediate and asynchronous.
Assuming that CE is set to 1, the two bits can select between the software power down options available. Setting
DB3 to 0 enables normal operation of the PLL. When (DB21, DB3) = (0,1), then the asynchronous power down
is selected, which means that the device powers down as soon as the programming is read. When (DB21, DB3)
= (1,1), then the synchronous power down is enabled. In this mode, the device enters power down on the next
cycle of the charge pump. This is a more controlled power down, as it avoids potential transients or erroneous
output frequencies.
MUXOUT
Bits DB4, DB5, and DB6 determine what signal appears at the output of the internal multiplexer, as described
in Table 5. For example, the most widely used output signal on this pin would be the digital lock detect signal,
which goes high when lock has been achieved. In order to program this mode, the user has to set (DB4, DB5,
DB6) = (1,0,0).
Charge Pump 3-state
DB8 of the function latch can set the output of the charge pump in a 3-state mode, if set to 1. Normal operation
of the device is attained when this bit is 0.
Fastlock Enable and Mode
Setting DB9 of the function latch to 1 enables the Fastlock Mode, whereas setting it to 0 deactivates this feature
altogether. Assuming that DB9 is 1, DB10 selects between the two possible Fastlock Modes: Fastlock Mode
1 is selected when DB10 is 0, whereas Fastlock Mode 2 is selected when DB10 is 1. The device actually enters
fastlock when the charge pump gain bit in the N counter latch (DB21) is set to 1. Once in Fastlock Mode 1, the
device switches back when DB21 of the N counter latch is set to 0. Conversely, once in Fastlock Mode 2, the
device switches back after the timeout condition has been reached, at which point DB21 of the N counter latch
is automatically set to 0.
Timer Counter Control
DB11DB14 of the function latch control the timer counter, in case the Fastlock Mode 2 was selected. These
four bits give the user the capability to program the number of PFD cycles that elapse before the device exits
the Fastlock Mode. Valid values for this are 3 to 63, in steps of 4 cycles. For example, programming (DB14,
DB13, DB12, DB11) = (0,0,1,0) results in 11 cycles before the Fastlock Mode times out.
Current Settings 1 and 2
DB15DB17 control the maximum charge pump current setting 1, while DB1820 control current setting 2. The
actual value of the maximum charge pump current will be dictated by the resistor placed outside on RSET (pin1).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TRF3750Q1900EVM | 功能描述:射頻開發(fā)工具 TRF3750Q1900 Eval Mod RoHS:否 制造商:Taiyo Yuden 產(chǎn)品:Wireless Modules 類型:Wireless Audio 工具用于評估:WYSAAVDX7 頻率: 工作電源電壓:3.4 V to 5.5 V |
| TRF3750Q2100EVM | 制造商:Texas Instruments 功能描述:TRF3750Q2100 EVAL - Bulk |
| TRF3750Q900EVM | 制造商:Texas Instruments 功能描述:TRF3750Q900 EVAL - Bulk |
| TRF3750T-1900EVM | 功能描述:射頻開發(fā)工具 TRF3750T-1900 Eval Mod RoHS:否 制造商:Taiyo Yuden 產(chǎn)品:Wireless Modules 類型:Wireless Audio 工具用于評估:WYSAAVDX7 頻率: 工作電源電壓:3.4 V to 5.5 V |
| TRF3761 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:INTEGER-N PLL WITH INTEGRATED VCO |
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