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參數(shù)資料
| 型號： | TRK-MPC5634M |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 13/122頁 |
| 文件大?。?/td> | 0K |
| 描述： | TRAK 5634M 144PN R2.1 |
| 設計資源： | TRK-MPC5634M Schematic |
| 標準包裝： | 1 |
| 系列： | MPC56xx |
| 類型： | MCU |
| 適用于相關產品： | MPC5634M |
| 所含物品： | 板，線纜，CD，DVD |
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Overview
MPC5634M Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
11
The CPU core has an additional ‘Wait for Interrupt’ instruction that is used in conjunction with low power STOP mode. When
Low Power Stop mode is selected, this instruction is executed to allow the system clock to be stopped. An external interrupt
source or the system wake-up timer is used to restart the system clock and allow the CPU to service the interrupt.
2.2.2
Crossbar
The XBAR multi-port crossbar switch supports simultaneous connections between three master ports and four slave ports. The
crossbar supports a 32-bit address bus width and a 64-bit data bus width.
The crossbar allows three concurrent transactions to occur from the master ports to any slave port; but each master must access
a different slave. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher
priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher
priority master completes its transactions. Requesting masters are treated with equal priority and are granted access to a slave
port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following
features:
3 master ports:
— e200z335 core complex Instruction port
— e200z335 core complex Load/Store port
—eDMA
4 slave ports
—FLASH
— calibration bus
—SRAM
— Peripheral bridge A/B (eTPU2, eMIOS, SIU, DSPI, eSCI, FlexCAN, eQADC, BAM, decimation filter, PIT, STM
and SWT)
32-bit internal address, 64-bit internal data paths
2.2.3
eDMA
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data
movements via 32 programmable channels, with minimal intervention from the host processor. The hardware micro architecture
includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,
along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation
is utilized to minimize the overall block size. The eDMA module provides the following features:
All data movement via dual-address transfers: read from source, write to destination
Programmable source and destination addresses, transfer size, plus support for enhanced addressing modes
Transfer control descriptor organized to support two-deep, nested transfer operations
An inner data transfer loop defined by a “minor” byte transfer count
An outer data transfer loop defined by a “major” iteration count
Channel activation via one of three methods:
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continuous transfers
— Peripheral-paced hardware requests (one per channel)
Support for fixed-priority and round-robin channel arbitration
Channel completion reported via optional interrupt requests
1 interrupt per channel, optionally asserted at completion of major iteration count
Error termination interrupts are optionally enabled
Support for scatter/gather DMA processing
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