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參數(shù)資料
| 型號： | TRU050-GKCNB-50M0000000 |
| 廠商： | VECTRON INTERNATIONAL |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, CDSO16 |
| 封裝： | ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, SMD-16 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大小： | 0K |
| 代理商： | TRU050-GKCNB-50M0000000 |
TRU050, VCXO Based PLL
Vectron International, 267 Lowell Rd, Hudson NH 03051-4916
Tel: 1-88-VECTRON-1
Web: www.vectron.com
Page 13 of 14
Rev: 26Aug2008
Figure 15. “Thru Hole Lead” Package
Table 7. Pin Functions
Pin
Symbol
Function
1
VC
VCXO Control Voltage
2
OPN
Op-Amp Negative Input
3
OPOUT
Op-Amp Output
4
OPP
Op-Amp Positive Input
5
LOSIN
INPUT (Used with LOS)
Logic 0, VCXO control voltage is enabled.
Logic 1, VCXO control voltage (pin 1) is disabled and OUT1 and OUT2 are within
+/-75 ppm of center frequency
Has Internal pull-down resistor
6
PHO
Phase detector output
7
DATAIN
Phase detector Input signal (TTL switching thresholds)
8
GND
Cover and Electrical Ground
9
CLKIN
Phase detector Clock signal (TTL switching thresholds)
10
LOS
OUTPUT (Used with LOSIN)
Logic 1 if there are no transitions detected at DATAIN after 256 clock cycles at
CLKIN. As soon as a transition occurs at DATAIN, LOS is set to logic low.
11
RCLK
Recovered Clock
12
RDATA
Recovered Data
13
Output 2
Divided-down VCXO Output, or No Output
14
HIZ
INPUT
Logic 0, OUT1, OUT2, RCLK, RDATA are set to a high impedance state.
Logic 1, OUT1, OUT2, RCLK, RDATA are active.
Has Internal pull-up resistor
15
Output 1
VCXO Output
16
VDD
Power Supply Voltage (3.3 V
±10% or 5.0 V ±10%)
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相關代理商/技術參數(shù) |
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| TRU050-GKCNB-65M0000000 | 制造商:VECTRON 制造商全稱:Vectron International, Inc 功能描述:Complete VCXO based Phase-Locked Loop |
| TRU050-GKLCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE DROP IN QUARTZ STABILIZED PLL SOLUTUION |
| TRU050-GKLFA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE DROP IN QUARTZ STABILIZED PLL SOLUTUION |
| TRU050-GKLGA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE DROP IN QUARTZ STABILIZED PLL SOLUTUION |
| TRU050-GKLGA-1M0000000 | 制造商:VECTRON 制造商全稱:Vectron International, Inc 功能描述:Complete VCXO based Phase-Locked Loop |
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