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    參數(shù)資料
    型號(hào): TRU050TDLNB49.152
    廠商: VECTRON INTERNATIONAL
    元件分類: PLL合成/DDS/VCOs
    英文描述: PHASE LOCKED LOOP, CDIP16
    封裝: ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, DIP-16
    文件頁(yè)數(shù): 7/14頁(yè)
    文件大小: 0K
    代理商: TRU050TDLNB49.152
    TRU050, VCXO Based PLL
    Vectron International, 267 Lowell Rd, Hudson NH 03051-4916
    Tel: 1-88-VECTRON-1
    Web: www.vectron.com
    Page 2 of 14
    Rev : 06Jan2006
    Performance Characteristics
    Table 1. Electrical Performance
    Parameter
    Symbol
    Min
    Typical
    Maximum
    Units
    Output Frequency (ordering option)
    Out 1, 5V option
    Out 1, 3.3V option
    1.000
    65.636
    51.840
    MHz
    Supply Voltage
    1
    +5
    +3.3
    VDD
    4.5
    3.0
    5.0
    3.3
    5.5
    3.6
    V
    Supply Current
    IDD
    65
    mA
    Output Logic Levels
    Output Logic High
    2
    Output Logic Low
    2
    VOH
    VOL
    2.5
    0.5
    V
    Output Transition Times
    Rise Time
    2
    Fall Time
    2
    tR
    tF
    5
    ns
    Input Logic Levels
    Output Logic High
    2
    Output Logic Low
    2
    VIH
    VIL
    2.0
    0.5
    V
    Loss of Signal Indication
    Output Logic High
    2
    Output Logic Low
    2
    VOH
    VOL
    2.5
    0.5
    V
    Nominal Frequency on Loss of Signal
    Output 1
    Output 2
    ±75
    ppm
    Symmetry or Duty Cycle
    3
    Out 1
    Out 2
    RCLK
    SYM1
    SYM2
    RCLK
    40/60
    45/55
    40/60
    %
    Absolute Pull Range, ordering option
    over operating temp, aging, power supply
    variations
    APR
    ±50
    ±80
    ±100
    ppm
    Test Conditions for APR (+5V option)
    VC
    0.5
    4.5
    V
    Test Conditions for APR (+3.3V option)
    VC
    0.3
    3.0
    V
    Gain Transfer
    Positive
    Phase Detector Gain
    +5V option
    +3.3V Option
    0.53
    0.35
    rad/V
    Operating temperature, ordering option
    0/70 or –40/85
    °C
    Control Voltage Leakage Current
    IVCXO
    ±1
    uA
    1. A good quality 0.01uF in parrallel with a 0.1 uf capacitor should be located as close to pin 16 to ground as possible.
    2. Figure 1 defines these parameters. Figure 2 illustrates the equivalent five-gate TTL load and operating conditions under which
    these parameters are tested and specified. Loads greater than 15 pF will adversely effect rise/fall time and duty cycle.
    3. Symmetry is defined as (ON TIME/PERIOD with Vs=-1.4 V for both 5V and 3.3V operation.
    Figure 2. Output Waveform
    Figure 3. OUT1, OUT2, RDATA and RCLK
    Test Conditions (25
    ±5°C)
    80
    %
    1.4V
    20
    %
    TF
    TR
    Period
    On Time
    +
    -
    +
    -
    IC
    VC
    3
    .1
    F.01F
    15pF
    16
    1
    IDD
    650
    VDD
    1.8k
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