- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄98287 > TS(X)8387VF_ 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 PDF資料下載
參數(shù)資料
| 型號(hào)： | TS(X)8387VF_ |
| 元件分類(lèi)： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁(yè)數(shù)： | 16/38頁(yè) |
| 文件大?。?/td> | 617K |
| 代理商： | TS(X)8387VF_ |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)當(dāng)前第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)
TS8387
23/38
6. DEFINITION OF TERMS
(BER)
Bit error rate
Probability to exceed a specified error threshold for a sample.
(BW)
Full power input
bandwidth
The analog input frequency at which the fundamental component in the digitally
reconstructed output has fallen by 3 dB with respect to its low frequency value
(determined by FFT analysis) for input at Full Scale.
(SINAD)
Signal to noise and
distortion ratio
The ratio expressed in dB of the RMS signal amplitude, set at 1dB below Full Scale,
to the RMS sum of all other spectral components, including the harmonics except DC.
(SNR)
Signal to noise ratio
The ratio expressed in dB of the RMS signal amplitude, set at 1dB below Full Scale,
to the RMS sum of all other spectral components excluding the five first harmonics.
(THD)
Total harmonic
distorsion
The ratio expressed in dBc of the RMS sum of the first five harmonic components, to
the RMS value of the measured fundamental spectral component.
(SFDR)
Spurious free
dynamic range
The ratio expressed in dB of the RMS signal amplitude, set at 1dB below Full Scale,
to the RMS value of the next highest spectral component (peak spurious spectral com-
ponent). SFDR is the key parameter for selecting a converter to be used in a frequency
domain application ( Radar systems, digital receiver, network analyzer ....)
(ENOB)
Effective Number Of
Bits
ENOB
+
SINAD –1.76
) 20 Log A
V 2
6.02
Where A is the actual input
amplitude and V is the full scale
range of the ADC under test
(DNL)
Differential non
linearity
The Differential Non Linearity for an output code i is the difference between the mea-
sured step size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL
is the maximum value of all DNL (i). DNL error specification of less than 1 LSB guaran-
tees that there are no missing output codes and that the transfer function is monotonic.
(INL)
Integral non linearity The Integral Non Linearity for an output code i is the difference between the measured
input voltage at which the transition occurs and the ideal value of this transition.
INL (i) is expressed in LSBs, and is the maximum value of all
|INL (i)|.
(DG)
Differential gain
The peak gain variation (in percent) at five different DC levels for an AC signal of 20%
Full Scale peak to peak amplitude. FIN = 5 MHz. (TBC)
(DP)
Differential phase
The peak Phase variation (in degrees) at five different DC levels for an AC signal of 20%
Full Scale peak to peak amplitude. FIN = 5 MHz. (TBC)
(TA)
Aperture delay
The delay between the rising edge of the differential clock inputs (CLK,CLKB) (zero
crossing point), and the time at which (VIN,VINB) is sampled.
(JITTER)
Aperture uncertainty The sample to sample variation in aperture delay. The voltage error due to jitter depends
on the slew rate of the signal at the sampling point.
(TS)
Settling time
Time delay to achieve 0.2 % accuracy at the converter output when a 80% Full Scale
step function is applied to the differential analog input.
(ORT)
Overvoltage recov-
ery time
Time to recover 0.2 % accuracy at the output, after a 150 % full scale step applied on
the input is reduced to midscale.
(TOD)
Output delay
The delay from the falling edge of the differential clock inputs (CLK,CLKB) (zero cross-
ing point) to the next point of change in the differential output data (zero crossing) with
specified load.
(TDR)
Data Ready output
delay
The delay from the rising edge of the differential clock inputs (CLK,CLKB) (zero crossing
point) to the rising edge of the differential Data Ready (DR,DRB) (zero crossing point)
output signal with specified load.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TS(X)8387MF | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS(X)8387MF_ | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS(X)8387MFB/C | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS(X)8387CF_ | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS(X)8387MF | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSX-8A16MHZ | 制造商:Epson Electronics America Inc 功能描述:CODE BCAI |
| TSX920ILT | 功能描述:General Purpose Amplifier 1 Circuit Rail-to-Rail SOT-23-6 制造商:stmicroelectronics 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 放大器類(lèi)型:通用 電路數(shù):1 輸出類(lèi)型:滿擺幅 壓擺率:17 V/μs 增益帶寬積:10MHz -3db 帶寬:- 電流 - 輸入偏置:10pA 電壓 - 輸入失調(diào):4mV 電流 - 電源:2.9mA 電流 - 輸出/通道:74mA 電壓 - 電源，單/雙（±）:4 V ~ 16 V 工作溫度:-40°C ~ 125°C 安裝類(lèi)型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商器件封裝:SOT-23-6 標(biāo)準(zhǔn)包裝:1 |
| TSX921ILT | 制造商:STMicroelectronics 功能描述:ANALOG AND AUDIO SYSTEMS - Tape and Reel 制造商:STMicroelectronics 功能描述:ANALOG and AUDIO SYSTEMS |
| TSX921IYLT | 制造商:STMicroelectronics 功能描述:IC OPAMP R-R 10MHZ SOT23-5 |
| TSX922IDT | 功能描述:General Purpose Amplifier 2 Circuit Rail-to-Rail 8-SO 制造商:stmicroelectronics 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 放大器類(lèi)型:通用 電路數(shù):2 輸出類(lèi)型:滿擺幅 壓擺率:17 V/μs 增益帶寬積:10MHz -3db 帶寬:- 電流 - 輸入偏置:10pA 電壓 - 輸入失調(diào):4mV 電流 - 電源:2.8mA 電流 - 輸出/通道:74mA 電壓 - 電源，單/雙（±）:4 V ~ 16 V 工作溫度:-40°C ~ 125°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商器件封裝:8-SO 標(biāo)準(zhǔn)包裝:1 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。