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| 型號： | TS(X)PC603EMGU/T2LN |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 80 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | CERAMIC, BGA-255 |
| 文件頁數(shù)： | 17/38頁 |
| 文件大?。?/td> | 632K |
| 代理商： | TS(X)PC603EMGU/T2LN |
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TSPC603E
24/38
5. FUNCTIONAL DESCRIPTION
5.1. PowerPC registers and programming model
The PowerPC architecture defines register-to-register operations for most computational instructions. Source operands for these
instructions are accessed from the registers or are provided as immediate values embedded in the instruction opcode. The three-reg-
ister instruction format allows specification of a target register distinct from the two source operands. Load and store instructions
transfer data between registers and memory.
PowerPC processors have two levels of privilege - supervisor mode of operation (typically used by the operating system) and user
mode of operation (used by the application software). The programming models incorporate 32 GPRs, 32 FPRs, special-purpose
registers (SPRs) and several miscellaneous registers. Each PowerPC microprocessor also has its own unique set of hardware
implementation (HID) registers.
Having access to privilege instructions, registers, and other resources allows the operating system to control the application environ-
ment (providing virtual memory and protecting operating-system and critical machine resources). Instructions that control the state of
the processor, the address translation mechanism, and supervisor registers can be executed only when the processor is operating in
supervisor mode.
The following sections summarize the PowerPC registers that are implemented in the 603e.
5.1.1. General-Purpose Registers (GPRs)
The PowerPC architecture defines 32 user-level, general-purpose registers (GPRs). These registers are either 32 bits wide in 32-bit
PowerPC microprocessors and 64 bits wide in 64-bit PowerPC microprocessors. The GPRs serve as the data source or destination
for all integer instructions.
5.1.2. Floating-Point Registers (FPRs)
The PowerPC architecture also defines 32 user-level, 64-bit floating-point registers (FPRs). The FPRs serve as the data source or
destination for floating-point instructions. These registers can contain data objects of either single - or double - precision floating-point
formats.
5.1.3. Condition Register (CR)
The CR is a 32-bit user-level register that consists of eight four-bit fields that reflect the results of certain operations, such as move,
integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching.
5.1.4. Floating-Point Status and Control Register (FPSCR)
The floating-point status and control register (FPSCR) is a user-level register that contains all exception signal bits, exception sum-
mary bits, exception enable bits, and rounding control bits needed for compliance with the IEEE 754 standard.
5.1.5. Machine State Register (MSR)
The machine state register (MSR) is a supervisor-level register that defines the state of the processor. The contents of this register
are saved when an exception is taken and restored when the exception handling completes. The 603e implements the MSR as a
32-bit register, 64-bit PowerPC processors implement a 64-bit MSR.
5.1.6. Segment Registers (SRs)
For memory management, 32-bit PowerPC microprocessors implement sixteen 32-bit segment registers (SRs). To speed access,
the 603e implements the segment registers as two arrays ; a main array (for data memory accesses) and a shadow array (for instruc-
tion memory accesses). Loading a segment entry with the Move to Segment Register (stsr) instruction loads both arrays.
5.1.7. Special-Purpose Registers (SPRs)
The powerPC operating environment architecture defines numerous special-purpose registers that serve a variety of functions, such
as providing controls, indicating status, configuring the processor, and performing special operations. During normal execution, a
program can access the registers, shown in Figure 15, depending on the program’s access privilege (supervisor or user, determined
by the privilege-level (PR) bit in the MSR). Note that register such as the GPRs and FPRs are accessed through operands that are
part of the instructions. Access to registers can be explicit (that is, through the use of specific instructions for that purpose such as
Move to Special-Purpose Register (mtspr) and Move from Special-Purpose Register (mfspr) instructions) or implicit, as the part of the
execution of an instruction. Some registers are accessed both explicitly and implicitly.
Il the 603e, all SPRs are 32 bits wide.
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