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參數(shù)資料
| 型號(hào)： | TS(X)PC603EMGU2ML |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 80 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | CERAMIC, BGA-255 |
| 文件頁數(shù)： | 14/38頁 |
| 文件大?。?/td> | 632K |
| 代理商： | TS(X)PC603EMGU2ML |
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TSPC603E
21/38
Num
Characteristic
80 MHz
100 MHz
120 MHz
133 MHz
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
17
SYSCLK to ABB, DBB, high impedance
after precharge
–
1.2
–
1.2
–
1.2
–
1.2
tsys
5, 7
18
SYSCLK to ARTRY high impedance
before precharge
–
9.0
–
9.0
–
9.0
–
9.0
ns
19
SYSCLK to ARTRY precharge enable
0.2 *
tsys
+ 1.0
–
0.2 *
tsys
+ 1.0
–
0.2 *
tsys
+ 1.0
–
0.2 *
tsys
+ 1.0
–
ns
3, 5,
8
20
Maximum dalay to ARTRY precharge
–
1.2
–
1.2
–
1.2
–
1.2
tsys
5, 8
21
SYSCLK to ARTRY high impedance
after precharge
–
2.25
–
2.25
–
2.25
–
2.25
tsys
5, 8
Notes:
1.
All output specifications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level (0.8 V or 2.0 V) of the signal in question.
Both input and output timings are measured at the pin. See.
2.
All maximum timing specifications assume CL = 50 pF.
3.
This minimum parameter assumes CL = 0 pF.
4.
SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external voltage from 5.5 V to 0.8 V instead
of from Vdd to 0.8 V (5 V CMOS levels instead of 3.3 V CMOS levels).
5. tsys is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
6.
Output signal transitions from GND to 2.0 V or Vdd to 0.8 V.
7.
Nominal precharge width for ABB and DBB is 0.5 tsysclk.
8.
Nominal precharge width for ARTRY is 1.0 tsysclk.
Figure 10 : Output timing diagram
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