- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄272328 > TS(X)PC603EVGU3LL 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 PDF資料下載
參數(shù)資料
| 型號： | TS(X)PC603EVGU3LL |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | CERAMIC, BGA-255 |
| 文件頁數(shù)： | 27/38頁 |
| 文件大?。?/td> | 632K |
| 代理商： | TS(X)PC603EVGU3LL |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
TSPC603E
33/38
5.5. Memory management
The following subsections describe the memory management features of the PowerPC architecture, and the 603e implementation,
respectively.
5.5.1. PowerPC memory management
The primary functions of the MMU are to translate logical (effective) addresses to physical addresses for memory accesses, and to
provide access protection on blocks and pages of memory.
There are two types of accesses generated by the 603e that require address translation - instruction accesses, and data accesses to
memory generated by load and store instructions.
The PowerPC MMU and exception model support demand-paged virtual memory. Virtual memory management permits execution of
programs larger than the size of physical memory ; demand-paged implies that individual pages are loaded into physical memory
from system memory only when they are first accessed by an executing program.
The hashed page table is a variable-sized data structure that defines the mapping between virtual page numbers and physical page
numbers. The page table size is a power of 2, and its starting address is a multiple of its size.
The page table contains a number of page table entry groups (PTEGs). A PTEG contains eight page table entries (PTEs) of eight
bytes each ; therefore, each PTEG is 64 bytes long. PTEG addresses are entry points for table search operations.
Address translations are enabled by setting bits in the MSR-MSR[IR] enables instruction address translations and MSR[DR] enables
data address translations.
5.5.2. PowerPC 603e microprocessor memory management
The instruction and data memory management units in the 603e provide 4 Gbyte of logical address space accessible to supervisor
and user programs with a 4-Kbyte page size and 256-Mbyte segment size. Block sizes range from 128 Kbyte to 256Mbyte and are
software selectable. In addition, the 603e uses an interim 52-bit virtual address and hashed page tables for generating 32-bit physical
addresses. The MMUs in the 603e rely on the exception processing mechanism for the implementation of the paged virtual memory
environment and for enforcing protection of designated memory areas.
Instruction and data TLBs provide address translation in parallel with the on-chip cache access, incurring no additional time penalty in
the event of a TLB hit. A TLB is a cache of the most recently used page table entries. Software is responsible for maintaining the
consistency of the TLB with memory. The 603e’s TLBs are 64-entry, two-way set-associative caches that contain instruction and data
address translations. The 603e provides hardware assist for software table search operations through the ashed page table on TLB
misses. Supervisor software can invalidate TLB entries selectively.
The 603e also provides independent four-entry BAT arrays for instructions and data that maintain address translations for blocks of
memory. These entries define blocks that can vary from 128 Kbyte to 256 Mbyte. The BAT arrays are maintained by system software.
As specified by the PowerPC architecture, the hashed page table is a variable-sized data structure that defines the mapping between
virtual page numbers and physical page numbers. The page table size is a power of 2, and its starting address is a multiple of its size.
Also as specified by the PowerPC architecture, the page table contains a number of page table entry groups (PTEGs). A PTEG con-
tains eight page table entries (PTEs) of eight bytes each ; therefore, each PTEG is 64 bytes long. PTEG addresses are entry points for
table search operations.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSPC603RVGSB/Q14LC | 32-BIT, 300 MHz, RISC PROCESSOR, CBGA255 |
| TSXPC603RVGB/Q14LC | 32-BIT, 300 MHz, RISC PROCESSOR, CBGA255 |
| TS80C31X2-LJER | 8-BIT, 30 MHz, MICROCONTROLLER, PQFP44 |
| TS80C32X2-ELCR | 8-BIT, MICROCONTROLLER, PQFP44 |
| TS80C31X2-VJBB | 8-BIT, 40 MHz, MICROCONTROLLER, PQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSXPC860SRVZQU66D | 功能描述:IC MPU POWERQUICC 66MHZ 357PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點:全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤 |
| TSXPCX1031 | 制造商:Schneider Electric 功能描述:CABLE TO PC SERIAL PORT (SUB-D9) 制造商:Schneider Electric 功能描述:PROGRAMMABLE CABLE 制造商:Schneider Electric 功能描述:MULTI-FUNCTION COMMUNICATION CABLE 制造商:Schneider Electric 功能描述:PROGRAMMABLE CABLE; Accessory Type:Programmable Cable; For Use With:Schneider Non-Ethernet Based Twido PLCs ;RoHS Compliant: Yes 制造商:Schneider Electric 功能描述:Programme cable for twido-nano-micro PLC |
| TSXPLP01 | 制造商:Schneider Electric 功能描述:BATTERY FOR TSX 37 制造商:Schneider Electric 功能描述:BATTERY FOR TSX 37 ;ROHS COMPLIANT: YES 制造商:Schneider Electric 功能描述:TSXPLP01 PLC replacement battery |
| TSXPLP101 | 制造商:Schneider Electric 功能描述:BATTERY TSX 37 QTY.10, TSXPLP101 |
| TSXPRGLDR | 制造商:Schneider Electric 功能描述:PROGRAM LOADER FOR 07/37 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。