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參數(shù)資料
| 型號： | TS12A4516P |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 多路復(fù)用及模擬開關(guān) |
| 英文描述： | 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 404K |
| 代理商： | TS12A4516P |
www.ti.com
APPLICATION INFORMATION
Power-Supply Considerations
Logic-Level Thresholds
Test Circuits/Timing Diagrams
NO
orNC
DUAL SUPPLY, LOW ON-STATE RESISTANCE
SPST CMOS ANALOG SWITCHES
SCDS236A – DECEMBER 2006 – REVISED MARCH 2007
The TS12A4516 and TS12A4517 operate with power-supply voltages from
±1 V to ±6 V [(2 V < (V
+ – V–) <
12 V], but are tested and specified at
±5V, ±3.3V, and ±1.8V supplies. The pin-compatible TS12A4514 and
TS12A4515 are recommended for use when only a single supply is desirable.
The TS12A4516 and TS12A4517 construction is typical of most CMOS analog switches, except that they have
only two supply pins: V+ and V–. V+ and V– drive the internal CMOS switches and set their analog voltage limits.
Reverse ESD-protection diodes are internally connected between each analog-signal pin and both V+ and V–.
One of these diodes conducts if any analog signal exceeds V+ or V–.
Virtually all the analog leakage current comes from the ESD diodes to V+ or V–. Although the ESD diodes on a
given signal pin are identical and, therefore, fairly well balanced, they are reverse biased differently. Each is
biased by either V+ or V– and the analog signal. This means their leakages will vary as the signal varies. The
difference in the two diode leakages to the V+ and V– pins constitutes the analog-signal-path leakage current. All
analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal.
This is why both sides of a given switch can show leakage currents of the same or opposite polarity.
There is no connection between the analog-signal paths and V+ or V–.
V+ and V– also power the internal logic and logic-level translators. The logic-level translators convert the logic
levels to switched V+ and V– signals to drive the analog signal gates.
The logic-level thresholds are CMOS compatible but not TTL compatible. As V+ is raised, the level threshold
increases slightly. When V+ reaches 12 V, the level threshold is about 3 V– above the TTL-specified high-level
minimum of 2.8 V, but still compatible with CMOS outputs.
CAUTION:
Do not connect the TS12A4516/TS12A4517 V+ to 3 V and then connect the
logic-level pins to logic-level signals that operate from 5-V supply. TTL levels
can exceed 3 V and violate the absolute maximum ratings, damaging the part
and/or external circuits.
Figure 1. Charge Injection
7
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS12A4517 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL SUPPLY, LOW ON-STATE RESISTANCE SPST CMOS ANALOG SWITCHES |
| TS12A4517D | 功能描述:模擬開關(guān) IC Lo-Vltg Lo On-St Resist SPST CMOS RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:2 開關(guān)配置:SPDT 開啟電阻（最大值）:0.1 Ohms 切換電壓（最大）: 開啟時間（最大值）: 關(guān)閉時間（最大值）: 工作電源電壓:2.7 V to 4.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-16 |
| TS12A4517DBVR | 功能描述:模擬開關(guān) IC Lo-Vltg Lo On-State Res SPST CMOS Ana Sw RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:2 開關(guān)配置:SPDT 開啟電阻（最大值）:0.1 Ohms 切換電壓（最大）: 開啟時間（最大值）: 關(guān)閉時間（最大值）: 工作電源電壓:2.7 V to 4.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-16 |
| TS12A4517DG4 | 功能描述:模擬開關(guān) IC Lo-Vltg Lo On-St Resist SPST CMOS RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:2 開關(guān)配置:SPDT 開啟電阻（最大值）:0.1 Ohms 切換電壓（最大）: 開啟時間（最大值）: 關(guān)閉時間（最大值）: 工作電源電壓:2.7 V to 4.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-16 |
| TS12A4517DR | 功能描述:模擬開關(guān) IC Lo-Vltg Lo On-St Resist SPST CMOS RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:2 開關(guān)配置:SPDT 開啟電阻（最大值）:0.1 Ohms 切換電壓（最大）: 開啟時間（最大值）: 關(guān)閉時間（最大值）: 工作電源電壓:2.7 V to 4.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-16 |
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