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TS61 Series
Voltage Detector
Oscillation Description (Continue)
5/7
Version: A07
OUTPUT CURRENT OSCILLATION WITH THE CMOS OUTPUT CONFIGURATION
Since the TS61 series are CMOS ICs, through current will flow when the IC’s internal circuit switching operates (during
release and detect operations). Consequently, oscillation is liable to occur as a result of drops in voltage at the through
current’s resistor (R
IN
) during release voltage operations (refer to diagram 2). Since hysteresis exists during detect
operation, oscillation is unlikely to occur.
Diagram 2: Oscillation in relation to through current
Function Description
1. When input voltage (V
IN
) rises above detect voltage (V
DF
), output voltage (V
OUT
) will be equal to V
IN
. (A condition of
high impedance exists with N-ch open drain output configurations).
2. When input voltage (V
IN
) falls below detect voltage (V
DF
), output voltage will be equal to the ground voltage (V
SS
).
3. When input voltage (V
IN
) falls to a level below that of the minimum operating voltage (V
MIN
), output will become
unstable. In this condition, V
IN
will equal the pulled-up output (should output be pull-up).
4. When input voltage (V
IN
) rises above the ground voltage (V
SS
) level, output will be unstable at levels below the
minimum operating voltage (V
MIN
). Between the V
MIN
and detect release voltage V
DR
level, the ground voltage (V
SS
)
level will be maintained.
5. When input voltage (V
IN
) rises above detect release voltage (V
DR
), output voltage (V
OUT
) will be equal to V
IN
. (A
condition of high impedance exists with N-ch open drain output configurations.)
6. The difference between V
DR
and V
DF
represents the hysteresis range.
Timing Chart