參數(shù)資料
型號： TS68020MF16
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： HCMOS 32-bit Virtual Memory Microprocessor
中文描述： 32-BIT, 16.67 MHz, MICROPROCESSOR, CQFP132
封裝： CERAMIC, QFP-132
文件頁數(shù)： 13/45頁
文件大小： 1256K
代理商： TS68020MF16
13
TS68020
2115A–HIREL–07/02
Notes:
1. This number can be reduced to 5 nanoseconds if the strobes have equal loads.
2. If the asynchronous setup time (= 47) requirements are satisfied, the DSACKx low to data setup time (= 31) and DSACKx
low to BERR low setup time (= 48) can be ignored. The data must only satisfy the data in to clock low setup time (= 27) for
the following clock cycle, BERR must only satisfy the late BERR low to clock setup time (= 27) for the following clock cycle.
3. This parameter specifies the maximum allowable skew between DSACK0 to DSACK1 asserted or DSACK1 to DSACK0
asserted pattern = 47 must be met by DSACK0 and DSACK1.
4. In the absence of DSACKx, BERR is an asynchronous input using the asynchronous input setup time (= 47).
5. DBEN may stay asserted on consecutive write cycles.
6. Actual value depends on the clock input waveform.
7. This pattern indicates the minimum high time for ECS and OCS in the event of an internal cache hit followed immediately by
a cache miss or operand cycle.
8. This specification guarantees operations with the 68881 co-processor, and defines a minimum time for DS negated to AS
asserted (= 13A). Without this parameter, incorrect interpretation of = 9A and = 15 would indicate that the 68020 does not
meet 68881 requirements.
9. This pattern allows the systems designer to guarantee data hold times on the output side of data buffers that have output
enable signals generated with DBEN.
10. Guarantees that an alternate bus master has stopped driving the bus when the 68020 regains control of the bus after an
arbitration sequence.
11. Cannot be tested. Provided for system design purposes only.
12. T
case
= -55
°
C and +130
°
C in a Power off condition under Thermal soak for 4 minutes or until thermal equilibrium. Electrical
parameters are tested “instant on” 100 m sec. after power is applied.
13. All outputs unload except for load capacitance. Clock = fmax,
LOW: HALT, RESET
HIGH: DSACK0, DSACK1, CDIS, IPL0-IPL2, DBEN, AVEC, BERR.
f
Frequency of Operation
8.0
16.67
12.5
20.0
12.5
25
MHz
t
RADC
R/W Asserted to Data Bus Impedance
Change
55
30
25
20
(11)
t
HRPW
RESET Pulse Width (Reset Instruction)
56
512
512
512
Clks
(11)
t
BNHN
BERR Negated to HALT Negated
(Rerun)
57
0
0
0
ns
(11)
t
GANBD
BGACK Negated to Bus Driven
58
1
1
1
Clks
(10)(11)
t
GNBD
BG Negated to Bus Driven
59
1
1
1
Clks
(10)(11)
Table 6.
Dynamic Electrical Characteristics (Continued)
Symbol
Parameter
Interval
Number
68020-16
68020-20
68020-25
Unit
Notes
Min
Max
Min
Max
Min
Max
相關(guān)PDF資料
PDF描述
TS68020MF20 HCMOS 32-bit Virtual Memory Microprocessor
TS68020MF25 HCMOS 32-bit Virtual Memory Microprocessor
TS68020VR16 HCMOS 32-bit Virtual Memory Microprocessor
TS68020VR25 HCMOS 32-bit Virtual Memory Microprocessor
TS68020DESC02YA MB 41C 27#20 14#16 SKT RECP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TS68020MF1B/C16 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:HCMOS 32-bit Virtual Memory Microprocessor
TS68020MF1B/C16ZAO 制造商:e2v Technologies 功能描述:0N MICRO CMOS MILITAIRE 32 BIT
TS68020MF1B/C20 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:HCMOS 32-bit Virtual Memory Microprocessor
TS68020MF1B/C25 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:HCMOS 32-bit Virtual Memory Microprocessor
TS68020MF20 功能描述:IC MPU 32BIT 20MHZ 132CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點:全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*