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參數(shù)資料
| 型號(hào)： | TS68040MR33A |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Third- Generation 32-bit Microprocessor |
| 中文描述： | 32-BIT, 33 MHz, MICROPROCESSOR, CPGA179 |
| 封裝： | CERAMIC, PGA-179 |
| 文件頁數(shù)： | 22/49頁 |
| 文件大?。?/td> | 1637K |
| 代理商： | TS68040MR33A |
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22
TS68040
2116A–HIREL–09/02
Notes:
1. All testing to be performed using worst-case test conditions unless otherwise specified.
2. The following pins are active low: AVEC, BG, BS, BR, CDIS, CIOUT, IPEND, IPLO, IPL1, IPL2, LOCK, LOCKE, MDIS, MI,
RST0, RSTI, TA, TBI, TCI, TEA, TIP, TRST, TS and W of R/W.
3. Maximum operating junction temperature (T
J
) = +125°. Minimum case operating temperature (T
C
) = -55°. This device is not
tested at T
C
= +125°. Testing is performed by setting the junction temperature T
J
= +125°and allowing the case and ambient
temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature.
4. The levels on CDIS, MDIS, and the IPL2-IPL0 signals enable or disable the multiplexed bus mode, data latch enable mode,
and driver impedance selection respectively.
44c
TTn Valid to BCLK (Setup)
6
8.5
ns
44d
R/W Valid to BCLK (Setup)
6
5
ns
44e
SCn Valid to BCLK (Setup)
10
11
ns
45
BCLK to Address SIZn, TTn, R/W, SCn Invalid (Hold)
2
2
ns
46
TS Valid to BCLK (Setup)
5
9
ns
47
BCLK to TS Invalid (Hold)
2
2
ns
49
BCLK to BB High Impedance (68040 Assumes Bus Mastership)
9
9
ns
51
RSTI Valid to BCLK
5
4
ns
52
BCLK to RSTI Invalid
Mode Select Setup to RSTI Negated
(4)
RSTI Negated to Mode Selects Invalid
(4)
2
2
ns
53
20
20
ns
54
2
2
ns
Table 15.
Input AC Timing Specifications (Figure 9 to Figure 15) (Continued)
-55°C
≤
T
C
≤
T
Jmax
; 4.75V
≤
V
CC
≤
5.25V unless otherwise specified
(1)(2)(3)(4)
Num
Characteristic
25 MHz
33 MHz
Unit
Min.
Max.
Min.
Max.
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