參數(shù)資料
型號(hào)： TS68882MF20
廠商： ATMEL CORP
元件分類(lèi)： 數(shù)學(xué)處理器
英文描述： CMOS Enhanced Floating-point Co-processor
中文描述： MATH COPROCESSOR, CQFP68
封裝： CERAMIC, QFP-68
文件頁(yè)數(shù)： 31/43頁(yè)
文件大?。?/td> 1414K
代理商： TS68882MF20
31
TS68882
2119A
–
HIREL
–
04/02
This interface is quite flexible and allows any addressing mode to be used with floating-
point instructions. For the TS68000 Family, these addressing modes include immediate,
postincrement, predecrement, data or address register direct, and the indexed/indirect
addressing modes of the TS68020/TS68030. Some addressing modes are restricted for
some instructions in keeping with the TS68000 Family architectural definitions (i.e., PC
relative addressing is not allowed for a destination operand).
The orthogonal instruction set of the TS68882, along with the flexible branches and
addressing modes, allows a programmer writing assembly language code, or a compiler
writer generating object or source code for the MPU/TS68882 device pair, to think of the
TS68882 as though it is part of the MPU. There are no special restrictions imposed by
the co-processor interface, and floating-point arithmetic is coded exactly like integer
arithmetic.
Address Bus (A0 through
A4)
These active-high address line inputs are used by the main processor to select the co-
processor interface register locations located in the CPU address space. These lines
control the register selection as listed in Table 10.
When the TS68882 is configured to operate over an 8-bit data bus, the A0 pin is used as
an address signal for byte accesses of the co-processor interface registers. When the
TS68882 is configured to operate over a 16- or 32-bit system data bus, both the A0 and
SIZE pins are strapped high and/or low as listed in Table 11.
Table 10.
Co-processor Interface Register Selection
A4-A0
Offset
Width
Type
Register
0000x
S00
16
Read
Response
0001x
S02
16
Write
Control
0010x
S04
16
Read
Save
0011x
S06
16
R/W
Restore
0100x
S08
16
-
(Reserved)
0101x
S0A
16
Write
Command
0110x
S0C
16
-
(Reserved)
0111x
S0E
16
Write
Condition
100xx
S10
32
R/W
Operand
1010x
S14
16
Read
Register select
1011x
S16
16
-
(Reserved)
110xx
S18
32
Read
Instruction Address
111xx
S1C
32
R/W
Operand Address
Table 11.
System Data Bus Size Configuration
A0
Size
Data bus
Low
8-bit
Low
High
16-bit
High
High
32-bit
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