參數(shù)資料
型號: TS68882MR25
廠商: ATMEL CORP
元件分類: 數(shù)學(xué)處理器
英文描述: CMOS Enhanced Floating-point Co-processor
中文描述: MATH COPROCESSOR, CPGA68
封裝: CERAMIC, PGA-68
文件頁數(shù): 10/43頁
文件大?。?/td> 1414K
代理商: TS68882MR25
10
TS68882
2119A
HIREL
04/02
Notes:
1. Test load, see Figure 5.
2. Capacitance is periodically sampled rather than 100% tested.
Dynamic (Switching)
Characteristics
The limits and values given in this section apply over the full case temperature range -
55
°
C to +125
°
C and V
CC
in the range 4.5V to 5.5V, See
AC Electrical Specification Def-
initions
on page 13.
The numbers (N
°
) refer to the timing diagrams. See Figure 4, Figure 6, Figure 7, Figure
8 and Figure 9.
Figure 4.
Clock Input Timing Diagram
Note:
Timing measurements are referenced to and from a low voltage of 0.8V and a high volt-
age of 2.0V, unless otherwise noted. The voltage swing through this range should start
outside, and pass through, the range such that the rise of fall will be linear between 0.8V
and 2.0V.
I
CC
Maximum Supply Current (V
CC
= 5.5V; CLK = f
max
; part in Reset)
Capacitance (V
IN
= 0, T
A
= 25
°
C, f = 1MHz)
(2)
136
mA
C
in
20
pF
C
L
Output Load Capacitance
130
pF
Table 5.
Static Characteristics
V
CC
= 5.0 V
DC
± 10%; GND = 0 V
DC
; Tc = -55/+125
°
C or -40/+85
°
C
Symbol
Parameter
Min
Max
Unit
Table 6.
AC Electrical Characteristics - Clock Input
V
CC
= 5.0 V
DC
± 10%; GND = 0 V
DC;
Tc = -55
°
C to +125
°
C (see Figure 4)
N
°
Parameter
16.67 MHz
20 MHz
25 MHz
33.33 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Frequency of Operation
8
16.67
12.5
20
12.5
25
16.7
33.33
MHz
1
Clck Time
60
125
50
80
40
80
30
60
ns
2, 3
Clock Pulse Width
24
95
20
54
15
59
14
66
ns
4, 5
Rise and Fall Times
5
5
4
3
ns
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