參數(shù)資料
型號(hào)： TS68HC901
廠商： 意法半導(dǎo)體
英文描述： HCMOS Multi-Function Peripheral(HCMOS多功能外圍)
中文描述： HCMOS多功能外設(shè)（HCMOS多功能外圍）
文件頁(yè)數(shù)： 23/42頁(yè)
文件大?。?/td> 368K
代理商： TS68HC901
put lines TA0 and TB0. These control registers are
shown in Figure 14.
UNIVERSAL SYNCHRONOUS / ASYN-
CHRONOUS RECEIVER-TRANSMITTER
The universal synchronous / asynchronous recei-
ver-transmitter(USART)isa single full-duplexserial
channel with a double-buffered receiver and trans-
mitter. There are separate receive and transmit
clocksandseparate receiveandtransmitstatusand
databytes.The receive and transmitsections are al-
so assigned separate interrupt channels. Each sec-
tion has both a normal condition interrupt channel
and an error condition interrupt channel. These
channels can be optionally disabled from interrup-
ting the processor and instead, DMA transfers can
beperformed usingthereceiver ready and transmit-
ter ready external CMFPsignals.
CHARACTER PROTOCOLS
The CMFP USART supports asynchronous and
with the aid of a polynomial generator checker
(PGC) supports byte synchronous character for-
mats.These formats are selected independently of
thedivide-by-one and divide-by-16 clock modes.
When the divide-by-one clock mode is selected,
synchronization must be accomplished externally.
Thereceiver will sample theserial data on therising
edge of thereceiver clock. In the divide-by-16 clock
mode, the data is sampled at mid-bit time to in-
crease transient noise rejection.
Also, when the divide-by-16 clock mode isselected,
theUSART resynchronization logic is enabled. This
logic increases the channel’s clock skew tolerance.
Whena validtransitionisdetected, aninternalcoun-
ter is reset to state zero. Transition checking isthen
inhibited until statefour. Thenatstate eight, thepre-
vious stateofthe transitionchecking logic isclocked
into the receive shift register.
ASYNCHRONOUS FORMAT
Variable word length and start / stop bit configura-
tions are available under software control for asyn-
chronous operation. The word length can be five to
eight bitsandone, oneand one-half, or two stopbits
canbeselected. Theuser can alsoselectodd,even,
or no parity. For character lengths of lessthan eight
bits, the assembled character will consist of the re-
quired number of data bits followed by zeros in the
unused bit positions and a parity bit, if parity is en-
abled.
In the asynchronous format, start bit detection is al-
ways enabled. New data is not shifted into the re-
ceive shift register until a zero bit isreceived. When
the divide-by-16 clock mode is selected, the false
start bit logic is also active. Any transition must be
stable for three positive receive clock edges to be
considered valid. Thenavalid zero-to-one transition
must not occur for at least eight additional positive
clock edges.
SYNCHRONOUS FORMAT
Whenthesynchronous character formatisselected,
the 8-bit synchronous character loaded into thesyn-
chronous character register iscomparedtoreceived
serial data until a match is found. Once synchroni-
zation is established, incoming data is clocked into
the receiver. The synchronous word will be conti-
nuously transmitted during an underrun condition.
All synchronous characters can be optionally strip-
ped from the receive buffer. Figure 15 shows the
synchronous character register.
The synchronous character is typically written after
the data word length is selected, since unused bits
in the synchronous character register are zeroed
out. When parity is enabled, synchronous word
lengthis the data word length plus one. The CMFP
will compute and append the parity bit for the syn-
chronous wordwhen a wordlength of eightis selec-
ted. However, if the word length is less than eight,
7
USART DATA REGISTER
0
UDR
(2Fh)
D7
D6
D5
D4
D3
D2
D1
D0
7
SYNCHRONOUS CHARACTER REGISTER
0
SCR
(27h)
D7
D6
D5
D4
D3
D2
D1
D0
Figure 16 :
TS68HC901
23/42
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