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| 型號： | TS80C188EC-13 |
| 元件分類： | 16位微控制器 |
| 英文描述： | 16-Bit Microprocessor |
| 中文描述： | 16位微處理器 |
| 文件頁數(shù)： | 14/57頁 |
| 文件大?。?/td> | 585K |
| 代理商： | TS80C188EC-13 |
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80C186EC/188EC, 80L186EC/188EC
Table 2. Pin Descriptions
(Continued)
Pin Name
Pin
Type
Input
Type
Output
States
Pin Description
P3.1/TXI1
O
D
H(X)/H(Q)
R(0)
I(Q)
P(X)
Transmit Interrupt
output goes active to indicate that
serial channel 1 has completed a transfer. TXI1 is
multiplexed with an output only Port function.
P3.0/RXI1
O
D
H(X)/H(Q)
R(0)
I(Q)
P(X)
Receive Interrupt
output goes active to indicate that
serial channel 1 has completed a reception. RXI1 is
multiplexed with an output only port function.
WDTOUT
O
D
H(Q)
R(1)
I(Q)
P(X)
WatchDog Timer OUTput
is driven low for four clock
cycles when the watchdog timer reaches zero. WDTOUT
may be ANDed with the power-on reset signal to reset the
processor when the watchdog timer is not properly reset.
P2.7/CTS1
P2.3/CTS0
I/O
A(L)
H(X)
R(Z)
I(X)
P(X)
Clear-To-Send
input is used to prevent the transmission
of serial data on the TXD signal pin. CTS1 and CTS0 are
multiplexed with an I/O Port function.
P2.6/BCLK1
P2.2/BCLK0
I/O
A(L)/
A(E)
H(X)
R(Z)
I(X)
P(X)
Baud CLocK
input can be used as an alternate clock
source for each of the integrated serial channels. The
BCLK inputs are multiplexed with I/O Port functions. The
BCLK input frequency cannot exceed
(/2
the operating
frequency of the processor .
P2.5/TXD1
P2.1/TXD0
I/O
A(L)
H(Q)
R(Z)
I(X)/I(Q)
P(X)
Transmit Data
output provides serial data information.
The TXD outputs are multiplexed with I/O Port functions.
During synchronous serial communications, TXD will
function as a clock output.
P2.4/RXD1
P2.0/RXD0
I/O
A(L)
H(X)/H(Q)
R(Z)
I(X)/I(Q)
P(X)
Receive Data
input accepts serial data information. The
RXD pins are multiplexed with I/O Port functions. During
synchronous serial communications, RXD is bi-directional
and will become an output for transmission of data (TXD
becomes the clock).
DRQ3:0
I
A(L)
D
DMA ReQuest
input pins are used to request a DMA
transfer. The timing of the request is dependent on the
programmed synchronization mode.
NOTES:
1. READY is A(E) for the rising edge of CLKOUT, S(E) for the falling edge of CLKOUT.
2. Pin names in parentheses apply to the 80C188EC/80L188EC.
14
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