參數(shù)資料
型號: TS80C31X2-LCCD
廠商: TEMIC SEMICONDUCTORS
英文描述: 8-bit CMOS Microcontroller 0-60 MHz
中文描述: 8位CMOS微控制器0-60兆赫
文件頁數(shù): 39/40頁
文件大?。?/td> 484K
代理商: TS80C31X2-LCCD
Rev. A - Mar. 19, 1999
39
Preliminary
TS80C31X2
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins
to float when a 100 mV change from the loaded V
OH
/V
OL
level occurs. I
OL
/I
OH
≥ ±
20mA.
7.4.13 Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two.
Figure 20. Clock Waveforms
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (T
A
=25
°
C fully loaded)
RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays
are incorporated in the AC specifications.
CLOCK
XTAL2
ALE
INTERNAL
STATE4
STATE5
STATE6
STATE1
STATE2
STATE3
STATE4
STATE5
EXTERNAL PROGRAM MEMORY FETCH
READ CYCLE
RD
WRITE CYCLE
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
PORT OPERATION
PSEN
P0
P2 (EXT)
P0
P2
P0
P2
WR
RXD SAMPLED
RXD SAMPLED
P0 PINS SAMPLED
P1, P2, P3 PINS SAMPLED
P1, P2, P3 PINS SAMPLED
P0 PINS SAMPLED
MOV DEST PORT (P1, P2, P3)
(INCLUDES INT0, INT1, TO, T1)
MOV DEST P0
OLD DATA
NEW DATA
DPL OR Rt OUT
DATA OUT
PCLOUT(EVENIFPROGRAM
MEMORY IS INTERNAL)
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
INDICATES DPH OR P2 SFR TO PCH TRANSITION
DPL OR Rt OUT
FLOAT
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
INDICATES DPH OR P2 SFR TO PCH TRANSITION
INDICATES ADDRESS TRANSITIONS
FLOAT
FLOAT
FLOAT
PCL OUT
PCL OUT
PCL OUT
DATA
SAMPLED
DATA
SAMPLED
DATA
SAMPLED
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
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