參數(shù)資料
型號: TS80C31X2-MIA
廠商: TEMIC SEMICONDUCTORS
英文描述: IC-8-BIT CMOS CPU
中文描述: 集成電路8位CMOS處理器
文件頁數(shù): 21/40頁
文件大?。?/td> 484K
代理商: TS80C31X2-MIA
Rev. A - Mar. 19, 1999
21
Preliminary
TS80C31X2
Table 10. IPH Register
IPH - Interrupt Priority High Register (B7h)
7
6
Reset Value = XXX0 0000b
Not bit addressable
5
4
3
2
1
0
-
-
-
PSH
PT1H
PX1H
PT0H
PX0H
Bit
Number
Bit
Mnemonic
Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
PSH
Serial port Priority High bit
PSH
0
0
1
1
PS
0
1
0
1
Priority Level
Lowest
Highest
3
PT1H
Timer 1 overflow interrupt Priority High bit
PT1H
0
0
1
1
PT1
0
1
0
1
Priority Level
Lowest
Highest
2
PX1H
External interrupt 1 Priority High bit
PX1H
0
0
1
1
PX1
0
1
0
1
Priority Level
Lowest
Highest
1
PT0H
Timer 0 overflow interrupt Priority High bit
PT0H
0
0
1
1
PT0
0
1
0
1
Priority Level
Lowest
Highest
0
PX0H
External interrupt 0 Priority High bit
PX0H
0
0
1
1
PX0
0
1
0
1
Priority Level
Lowest
Highest
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