參數(shù)資料
型號(hào)： TS80C31X2-MIC
廠商： Atmel
文件頁(yè)數(shù)： 40/42頁(yè)
文件大小： 0K
描述： IC MCU 8BIT 40/20MHZ 44-PQFP
標(biāo)準(zhǔn)包裝： 27
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40/20MHz
連通性： UART/USART
外圍設(shè)備： POR
輸入/輸出數(shù)： 32
程序存儲(chǔ)器類型： ROMless
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-QFP
包裝： 托盤
7
4428E–8051–02/08
AT/TS80C31X2
6.
TS80C31X2 Enhanced Features
In comparison to the original 80C31, the TS80C31X2 implements some new features, which
are:
The X2 option.
The Dual Data Pointer.
The 4 level interrupt priority system.
The power-off flag.
The ONCE mode.
Enhanced UART
6.1
X2 Feature
The TS80C31X2 core needs only 6 clock periods per machine cycle. This feature called ”X2”
provides the following advantages:
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
Save power consumption while keeping same CPU power (oscillator power saving).
Save power consumption by dividing dynamically operating frequency by 2 in operating and
idle modes.
Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 sig-
nal and the main clock input of the core (phase generator). This divider may be disabled by
software.
6.1.1
Description
The clock for the whole circuit and peripheral is first divided by two before being used by the
CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2
mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to
60%. Figure 6-1. shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 ris-
ing edge to avoid glitches when switching from X2 to STD mode. Figure 6-2. shows the mode
switching waveforms.
Figure 6-1.
Clock Generation Diagram
XTAL1
2
CKCON reg
X2
state machine: 6 clock cycles.
CPU control
FOSC
F
XTAL
0
1
XTAL1:2
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