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參數(shù)資料
| 型號： | TS80C51RD2-MCLB |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 40 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 56/74頁 |
| 文件大?。?/td> | 689K |
| 代理商： | TS80C51RD2-MCLB |
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6
Rev. C - 06 March, 2001
TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
Mnemonic
Pin Number
Type
Name And Function
DIL
LCC
VQFP 1.4
VSS
20
22
16
I
Ground: 0V reference
Vss1
1
39
I
Optional Ground: Contact the Sales Ofce for ground connection.
VCC
40
44
38
I
Power Supply: This is the power supply voltage for normal, idle and power-
down operation
P0.0-P0.7
39-32
43-36
37-30
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them oat and can be used as high impedance inputs. Port 0 pins must
be polarized to Vcc or Vss in order to prevent any parasitic current consumption.
Port 0 is also the multiplexed low-order address and data bus during access to
external program and data memory. In this application, it uses strong internal
pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM
programming. External pull-ups are required during program verication during
which P0 outputs the code bytes.
P1.0-P1.7
1-8
2-9
40-44
1-3
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 1 pins that are externally pulled low will
source current because of the internal pull-ups. Port 1 also receives the low-order
address byte during memory programming and verication.
Alternate functions for Port 1 include:
1
2
40
I/O
T2 (P1.0): Timer/Counter 2 external count input/Clockout
2
3
41
I
T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control
3
4
42
I
ECI (P1.2): External Clock for the PCA
4
5
43
I/O
CEX0 (P1.3): Capture/Compare External I/O for PCA module 0
5
6
44
I/O
CEX1 (P1.4): Capture/Compare External I/O for PCA module 1
6
7
45
I/O
CEX0 (P1.5): Capture/Compare External I/O for PCA module 2
7
8
46
I/O
CEX0 (P1.6): Capture/Compare External I/O for PCA module 3
8
9
47
I/O
CEX0 (P1.7): Capture/Compare External I/O for PCA module 4
P2.0-P2.7
21-28
24-31
18-25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 2 pins that are externally pulled low will
source current because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Some Port 2 pins (P2.0 to P2.5) receive the high order address bits during
EPROM programming and verication:
P3.0-P3.7
10-17
11,
13-19
5,
7-13
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 3 pins that are externally pulled low will
source current because of the internal pull-ups. Some Port 3 pins (P3.4 to P3.5)
receive the high order address bits during EPROM programming and verication.
Port 3 also serves the special features of the 80C51 family, as listed below.
10
11
5
I
RXD (P3.0): Serial input port
11
13
7
O
TXD (P3.1): Serial output port
12
14
8
I
INT0 (P3.2): External interrupt 0
13
15
9
I
INT1 (P3.3): External interrupt 1
14
16
10
I
T0 (P3.4): Timer 0 external input
15
17
11
I
T1 (P3.5): Timer 1 external input
16
18
12
O
WR (P3.6): External data memory write strobe
17
19
13
O
RD (P3.7): External data memory read strobe
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TS80C51RD2-MCLD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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| TS80C51RD2-MCMB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TS80C51RD2-MCMD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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