參數(shù)資料
型號: TS80C51RD2-VIA
廠商: Atmel
文件頁數(shù): 6/84頁
文件大小: 0K
描述: IC MCU 8BIT 768BYTE 40MHZ 40-DIP
標(biāo)準(zhǔn)包裝: 216
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40/30MHz
連通性: UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器類型: ROMless
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
DS70292G-page 16
2007-2012 Microchip Technology Inc.
SCL1
SDA1
ASCL1
ASDA1
I/O
ST
No
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
TMS
TCK
TDI
TDO
I
O
ST
No
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
C1RX
C1TX
I
O
ST
Yes
ECAN1 bus receive pin.
ECAN1 bus transmit pin.
RTCC
O
No
Real-Time Clock Alarm Output.
CVREF
O
ANA
No
Comparator Voltage Reference Output.
C1IN-
C1IN+
C1OUT
I
O
ANA
No
Yes
Comparator 1 Negative Input.
Comparator 1 Positive Input.
Comparator 1 Output.
C2IN-
C2IN+
C2OUT
I
O
ANA
No
Yes
Comparator 2 Negative Input.
Comparator 2 Positive Input.
Comparator 2 Output.
PMA0
PMA1
PMA2 -PMPA10
PMBE
PMCS1
PMD0-PMPD7
PMRD
PMWR
I/O
O
I/O
O
TTL/ST
TTL/ST
No
Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and
Output (Master modes).
Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and
Output (Master modes).
Parallel Master Port Address (Demultiplexed Master Modes).
Parallel Master Port Byte Enable Strobe.
Parallel Master Port Chip Select 1 Strobe.
Parallel Master Port Data (Demultiplexed Master mode) or Address/
Data (Multiplexed Master modes).
Parallel Master Port Read Strobe.
Parallel Master Port Write Strobe.
DAC1RN
DAC1RP
DAC1RM
O
No
DAC1 Right Channel Negative Output.
DAC1 Right Channel Positive Output.
DAC1 Right Channel Middle Point Value (typically 1.65V).
DAC1LN
DAC1LP
DAC1LM
O
No
DAC1 Left Channel Negative Output.
DAC1 Left Channel Positive Output.
DAC1 Left Channel Middle Point Value (typically 1.65V).
COFS
I/O
ST
Yes
Data Converter Interface frame synchronization pin.
CSCK
I/O
ST
Yes
Data Converter Interface serial clock input/output pin.
CSDI
I
ST
Yes
Data Converter Interface serial data input pin
CSDO
O
Yes
Data Converter Interface serial data output pin.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
No
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
MCLR
I/P
ST
No
Master Clear (Reset) input. This pin is an active-low Reset to the
device.
AVDD
P
No
Positive supply for analog modules. This pin must be connected at all
times.
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
Type
PPS
Description
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
PPS = Peripheral Pin Select
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