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參數(shù)資料
| 型號(hào)： | TS80C52X2-LLCB |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 48/83頁(yè) |
| 文件大?。?/td> | 8336K |
| 代理商： | TS80C52X2-LLCB |
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47
32117D–AVR-01/12
AT32UC3C
The 3.3V regulator is connected to the 5V source (VDDIN_5 pin) and its output feeds the USB
pads. If the USB is not used, the 3.3V regulator can be disabled through the VREG33CTL field
of the VREGCTRL SCIF register.
Figure 6-1 on page 47 shows the power schematics to be used for 5V single supply mode. All
I/O lines and analog blocks will be powered by the same power (VDDIN_5 = VDDIO1 = VDDIO2
= VDDIO3 = VDDANA).
Figure 6-1.
5V Single Power Supply mode
6.1.3.2
3.3V Single Supply Mode
In 3.3V single supply mode, the VDDIN_5 and VDDIN_33 pins should be connected together
externally. The 1.8V internal regulator is connected to the 3.3 V source (VDDIN_5 pin) and its
output feeds VDDCORE.
The 3.3V regulator should be disabled once the circuit is running through the VREG33CTL field
of the VREGCTRL SCIF register.
Figure 6-2 on page 48 shows the power schematics to be used for 3.3V single supply mode. All
I/O lines and analog blocks will be powered by the same power (VDDIN_5 = VDDIN_33 =
VDDIO1 = VDDIO2 = VDDIO3 = VDDANA).
VDDIO1
VDDIO2
VDDIO3
CPU
Peripherals
Memories
SCIF, BOD,
RCSYS
3.3V
Reg
+
-
Analog: ADC, AC, DAC, ...
VDDIN_5
VDDANA
GNDANA
VDDCORE
COUT2
COUT1
GNDCORE
GNDPLL
PLL
GNDIO1
GNDIO2
GNDIO3
BOD50
BOD18
BOD33
1.8V
Reg
POR
CIN2
CIN1
VDDIN_33
COUT2
COUT1
4.5-
5.5V
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