參數(shù)資料
型號(hào): TS87C58X2-MIC
廠商: Atmel
文件頁數(shù): 18/62頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 32K OTP 40MHZ 44PQFP
標(biāo)準(zhǔn)包裝: 960
系列: 87C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40/20MHz
連通性: UART/USART
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-QFP
包裝: 托盤
25
4431E–8051–04/06
AT/TS8xC54/8X2
10. Interrupt System
The TS80C54/58X2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1),
three timer interrupts (timers 0, 1 and 2) and the serial port interrupt. These interrupts are shown
Figure 10-1. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit
in the Interrupt Enable register (See Table 10-2.). This register also contains a global disable bit,
which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by
setting or clearing a bit in the Interrupt Priority register (See Table 10-3.) and in the Interrupt Pri-
ority High register (See Table 10-4.). shows the bit values and priority levels associated with
each combination.
Table 10-1.
Priority Level Bit Values
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior-
ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.
IE1
0
3
High priority
interrupt
Interrupt
polling
sequence, decreasing from
high to low priority
Low priority
interrupt
Global Disable
Individual Enable
EXF2
TF2
TI
RI
TF0
INT0
INT1
TF1
IPH, IP
IE0
0
3
0
3
0
3
0
3
0
3
IPH.x
IP.x
Interrupt Level Priority
0
0 (Lowest)
01
1
10
2
1
3 (Highest)
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