參數(shù)資料
型號(hào)： TS87C58X2-VIC
廠商： Atmel
文件頁數(shù)： 26/62頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 32K OTP 40MHZ 44PQFP
標(biāo)準(zhǔn)包裝： 960
系列： 87C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40/30MHz
連通性： UART/USART
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-QFP
包裝： 托盤
32
4431E–8051–04/06
AT/TS8xC54/8X2
Table 12-2.
WDTPRG Register
WDTPRG Address (0A7h)
Reset value XXXX X000
12.1.1
WDT during Power Down and Idle
In Power Down mode the oscillator stops, which means the WDT also stops. While in Power
Down mode the user does not need to service the WDT. There are 2 methods of exiting Power
Down mode: by a hardware reset or via a level activated external interrupt which is enabled prior
to entering Power Down mode. When Power Down is exited with hardware reset, servicing the
WDT should occur as it normally should whenever the TS80C54/58X2 is reset. Exiting Power
Down with an interrupt is significantly different. The interrupt is held low long enough for the
oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the
WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the
interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best
to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
TS80C54/58X2 while in Idle mode, the user should always set up a timer that will periodically
exit Idle, service the WDT, and re-enter Idle mode.
7
6
5
4
3
2
1
0
T4
T3
T2
T1
T0
S2
S1
S0
Bit
Number
Bit
Mnemonic
Description
7
T4
Reserved
Do not try to set or clear this bit.
6
T3
5
T2
4
T1
3
T0
2
S2
WDT Time-out select bit 2
1
S1
WDT Time-out select bit 1
0
S0
WDT Time-out select bit 0
S2S1
S0
Selected Time-out
00
0
(214 - 1) machine cycles, 16.3 ms @ 12 MHz
00
1
(215 - 1) machine cycles, 32.7 ms @ 12 MHz
01
0
(2
16 - 1) machine cycles, 65.5 ms @ 12 MHz
01
1
(217 - 1) machine cycles, 131 ms @ 12 MHz
10
0
(218 - 1) machine cycles, 262 ms @ 12 MHz
10
1
(2
19 - 1) machine cycles, 542 ms @ 12 MHz
11
0
(220 - 1) machine cycles, 1.05 s @ 12 MHz
11
1
(221 - 1) machine cycles, 2.09 s @ 12 MHz
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